隨著元件縮小，穿遂電流大幅提昇，High-K已是目前半導體產業相當熱門的一項議題，但是使用了High-K卻會對元件產生非預期的FIBL效應。本論文透由模擬軟體，模擬元件使用High-K材料後的FIBL效應，並提出高於K值50之後，FIBL效應會加劇約2.8倍。以及其他相關改善的方法，包含堆疊結構或是新的元件DTMOS的使用，也將探討熱門基板材料Ge搭配High-K會有較佳的效果，並模擬其它材料特性對其搭配High-K材料的影響，包含基底材料和High-K本身的電子遷移率、能隙大小以及能態密度跟電子親和力等，發現到Ge基底抑制FIBL材料是根據能隙較小和DOS較大的原因，而High-K材料本身能隙大小也是其影響的重要因素，真實High-K材料能隙較小，FIBL亦比模擬要為嚴重。
而積體電路的另一重要分支便是記憶體，因此在論文的另一部份便是模擬快閃記憶體（Flash），並提出使用High-K材料可在相同EOT提高電荷保持力，以及面臨的困難有影響寫入跟抹除的能力。最後驗證新的元件結構『非對稱』（High-K/Low-k）和『對稱』（Low-K/High-K/Low-K）改善其問題，利用非對稱結構可大幅提昇寫入效率但抹除卻改善不多，而對稱結構卻可改善非對稱的缺陷。此外我們也模擬在上層絕緣層改用High-K材料，對其提高寫入和抹除效率，做其電荷耦合比和能障的討論，得到結論在上層固定EOT情形下，K值小於20會有最佳的效果。

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