本研究提出在 H.264/AVC 高階檔次影像解碼器的反相變動長度解碼、反相量化轉換及反相離散餘絃轉換的全硬體架構設計。離散餘絃轉換為影像編解碼器不可或缺的視頻轉換方法，透過此方法可以將存在於時域(Time Domain)的訊號轉換至頻域(Frequency Domain)以簡化後續的運算複雜度。在H.264/AVC 高階檔次影像解碼器的規範文件中，主要定義了兩種區塊大小的反相離散餘絃轉換方法，分別為四乘四區塊大小的轉換方式與八乘八區塊大小的轉換方式，針對不同影像特色的區塊採用不同大小轉換方式可以使得壓縮後的影像串流在相同的畫質之下達到更低的資料傳輸。而在此研究設計中，包含一個反相變動長度解碼器、一個二級管線架構的反相量化解碼器，以及一個二級管線架構並支援四乘四區塊與八乘八區塊運算之反相離散轉換解碼器。在所需的晶片面積方面，此設計在採用台積電零點一三微米製程元件之下，需要三十一千邏輯閘，運作於一百佰萬赫茲(MHz)。在整體效能方面，此設計作品具備三項特色：(1) 特殊設計的反向變動長度解碼器使整體作品節省50%的資料傳輸量。(2) 支援兩種區塊大小的反相離散餘絃轉換器並符合高階檔次影像解碼器的規範。(3) 支援四倍於高清晰度(4 x HD / QFHD)影像的即時逆離散解碼運算。此作品亦成功整合在本實驗室的多媒體即時解碼播放系統中，透過整合的方式更進一步確認作品的功能正確性。

We propose a pure hardware implementation of inverse quantization and inverse discrete cosine transform for H.264/AVC high profile video decoding. The proposed design supports 4x4 transform, 2x2/4x4 hadamard transform and 8x8 transform. It includes a run level decoder, a two-stage pipelined architecture for inverse quantization, and a two-stage pipelined architecture for inverse discrete cosine transform. The proposed design is both area-efficient (31K gates) and high performance (100MHz @ TSMC .13 μm). It can support real-time decoding of 3840 x 2160 video @ 30 fps. The design has not only passed gate level simulation but also integrated into a multimedia SoC platform.

[1]. Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC)
[2]. JVT H.264/AVC Reference Software JM 9.0
[3]. Kuan-Hung Chen, Jiun-In Guo, and Jinn-Shyan Wang “A High-Performance Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264”, IEEE Transactions on Circuits and Systems for Video Technology, Page(s): 472- 483, April 2006
[4]. Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, and Jar-Ferr Yang “Combined 2-D Transform and Quantization Architectures for H.264 Video Coders”, IEEE Transactions on Circuits and Systems for Video Technology, Page(s): 1802 - 1805, May 2005
[5]. Ihab Amer, Wael Badawy, and Graham Jullien “A High-Performance Hardware Implementation of the H.264 Simplified 8x8 Transform and Quantization”, IEEE International Conference on Acoustics, Speech, and Signal Processing, Page(s): ii/1137 - ii/1140 Vol. 2, March 2005
[6]. Yu-Kun Lin, Ying-Ze Liao, and Tian-Sheuan Chang “An Area-efficient Design for Integer Transform in H.264/AVC FRExt”, The 17th VLSI Design/CAD Symposium, 2006
[7]. TrasnEDA Verification Navigator
http://www.transeda.com
[8]. TSMC 0.13 μm standard cell library
http://www.tsmc.com/english/b_technology/b01_platform/b010102_013um.htm
[9]. Synplify Pro, Synplicity
http://www.synplicity.com/products/synplifypro/index.html
[10]. Quartus II, Altera Corporation
http://www.altera.com/products/software/products/quartus2/qts-index.html
[11]. ISE, Xilinx Corporation
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
[12]. Design Compiler, Synopsys Corporation
http://www.synopsys.com/products/logic/design_compiler.html
[13]. NC-Verilog, Cadence Corporation
http://www.cadence.com/products/functional_ver/nc-verilog/index.aspx