現今電子產品發展朝向高功率、高密度、可靠度佳以及微小化等特性發展，在眾多的封裝結構中晶圓級晶片尺寸封裝(Wafer Level Chip Size Packaging, WLCSP)同時具備了以上特性。對於WLCSP而言由於其結構在晶片及錫球間具有緩衝層結構設計，緩衝層可減少錫球之受力並延長其壽命，因此不同於覆晶封裝(Flip Chip Packaging)，WLCSP是不需要充填底膠(underfill)結構的。少了底膠的保護，若結構設計不良，則WLCSP封裝會因為晶片與基板之間熱膨脹係數不匹配造成過高的熱應變及熱應力而使得錫球接點提早破壞。通常評估WLCSP可靠度的測試實驗會花費許多時間及金錢，若能將WLCSP準確以有限元素法分析，其模擬結果將可取代實驗，並大幅縮短產品研發之時程。本研究將以有限元素模擬法對WLCSP進行分析探討。
近年來為了降低可靠度測試時間，將負載設定成更嚴苛的環境，使得測試載具提前失效以達成加速測試之目的。根據JEDEC標準測試規範，常用的溫度測試範圍為-40°C到125°C，因此本研究採用此範圍進行模擬分析。在加速熱循環負載測試中，溫度通常都超過焊錫材料熔點絕對溫度(K)的三分之一，因此在此過程中即會發生較為顯著的潛變效應，造成潛變應變的累積。
對於加速熱循環負載型式而言，提高升降溫速率對於縮短測試時間是常被使用的方法。然而升降溫速率提高會使得材料應變率上升，造成材料強度的變化，而潛變也會因升溫速率的提高，使得在整體溫度循環中之升降溫段時間減少，造成較少的潛變應變累積。由於潛變應變累積較小伴隨鬆弛現象的降低，使得在結束升降溫段有較高之應力，高應力就容易使得材料在熱循環過程中進入塑性區。由此可知升溫速率的改變對於可靠度具有一定程度的影響。此外，在溫度循環過程中持溫時間對於可靠度的影響也非常重要，因為當持溫時間越長則產生的潛變應變越多，使得錫球壽命降低，因此如何對其行為進行精準的評估是相當重要的。
本研究中將以兩種不同理論，分析在加速熱循環條件下潛變及塑性應變之相關行為，這兩種理論分別為Anand 模型以及Garofalo 雙曲正弦模型搭配Chaboche動態硬化模型來描述潛變及塑性應變行為。由分析結果可知使用這兩組理論進行分析將會得到相同的應變累積趨勢。
其中本研究中還探討了兩種不同壽命預估模型在不同升降溫速率之可靠度評估，其中兩種壽命預估模型分別為Coffin-Manson 應變法以及Darveaux能量密度法，經由模擬結果顯示在改變升降溫速率時等效非彈性應變增量不明顯，將此結果代入Coffin-Manson 應變法無法呈現實驗結果的趨勢，但是將應變能密度結果代入Darveaux能量密度法模型，其趨勢則與實驗結果相符。此外，若加速熱循環條件為固定升降溫速率及改變持溫時間，則可以發現將其結果分別代入Coffin-Manson 應變法以及Darveaux能量密度法皆可獲得與實驗結果相同的趨勢。
對於Norris-Landzberg所提出之加速因子(Acceleration Factor, AF)而言未將潛變效應納入考量，因此若將改變升降溫速率之結果代入此公式將會預估出違背實驗及模擬結果。本研究最後將提出修正型之加速因子公式並將潛變納入考量，使其計算結果符合實驗及模擬結果。

Nowadays, electronic packaging has developed to achieve high power, high I/O, good reliability performance and small form factor characteristics. Among the various packages have been adopted by industry, Wafer Level Chip Size Packaging (WLCSP) fulfills above demands. Unlike flip chip packaging, WLCSP does not need underfill protection since it possesses a soft stress buffer layer between silicon chip and solder bump, the buffer layer can reduce the stress/strain in solder joint and prolong its lifetime. However, no underfill protection induced the high stress/strain which is caused by coefficient of thermal expansion mismatch (CTE) in thermal loading. This effect allows WLCSP failure more easily. In general, using experiments to assess reliability of WLCSP will take much time and money, so the finite element method and design-on-simulation technology have been widely used for predicting the thermal fatigue life of packaging under thermal cycling loading condition. If the simulation results are exact to match the experiments, this simulation can substitute the experiments to progress some analysis such as parameter designs, fatigue life prediction, etc. Using finite element method would spend less time than conduct some experiments, so this research gives finite element method of WLCSP to analyze creep effect and discuss various thermal cycling loading conditions.
In order to reduce the development time and ensure the reliability quality of electronic packaging, the Accelerated Thermal Cycling Test (ATC) is a standard method which is currently used to characterize the reliability performance of electronic packaging. The most commonly used temperature range for commercial electronic products is from -40°C to 125°C, and within a predefined temperature range the creep effect is more significant in the solder material because the homologous temperature is excessed to 0.33 Tm (in K) in the thermal cycling loading. According to the simulation result, it can be found the creep effect is the main factor that caused the solder to failure.
The increase in the ramp rate of the thermal cycling loading is often used to reduce test duration, but increase in the ramp rate causes the material to change its stress/strain properties. In addition, creep effect becomes smaller in the ramp section of thermal cycling because it allows lesser time in the ramp section of thermal cycling. Due to increasing ramp rate, it causes a less creep effect, so the stress relaxation effect also becomes less. Because of the less stress relaxation effect, it makes the materials have more stress at the end of ramp section that allows the materials to produce plastic strain more easily. To sum up, changing the ramp rate in the thermal cycling loading influences the reliability of electronic packaging. On the other hand, the dwell time of thermal cycling also affects the reliability of materials because increases in the dwell time that causes more creep strain and has less fatigue cycles in the solder material. According to the above discussion, it is very important to use an exact simulation method to assess the reliability of electronic packaging.
In this study, the Anand Model and the Garofalo Hyperbolic Sine Model with Chaboche Kinematic Hardening Model are used to simulate creep and plasticity behavior in the simulation process. The results of simulation indicates that both of them have the same tendency during thermal cycling loading.
There are two standard methods to calculate the predict fatigue cycles such as Coffin-Mason strain based model and Darveaux energy based model. The results of simulation demonstrate that the incremental inelastic strain is changed insignificantly, so the fatigue cycle can’t coincide with the experimental results which are calculated by using Coffin-Mason strain based model. In addition, the incremental energy density is increased when the ramp rate is increased. Substituting this results to Darveaux energy based model would get the life prediction cycles which is agreed with the experiment results. Moreover, in the case of fixed ramp rate and varied the dwell time, the life prediction cycles which are calculated by both models and have the same tendency of the life predicted cycles.
In Norris-Landzberg Acceleration Factor Model, it doesn’t consider creep effect in this formula, so it will predict a violation result when using the experimental data which are progressed on fixed dwell time and various ramp rate in thermal cycling test. Finally, the modified AF formula which considers the creep effect will be proposed. As a result, the life prediction cycle which is calculated by the modified AF formula is corresponded with all of experimental results.

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