在下一個世代的無線通訊系統，為提高資料傳輸率，結合多輸入多輸出(Multiple-input multiple-output, MIMO)訊號處理與正交分頻多工(orthogonal frequency-division multiplexing, OFDM) 是個趨勢。IEEE 802.11n標準以多輸出多輸入正交分頻多工(MIMO OFDM)系統為基礎，將傳輸率(data rate)從原來的54Mb/s提高到600Mb/s。一個IEEE802.11n的接收器可提供6到630Mb/s的資料傳輸率，64/128個副載波傳輸訊號的頻寬是20/40MHz，天線的數目是1到4，快速傅利葉轉換處理器/反快速傅利葉轉換處理器的數目也需要1到4個，所以所需硬體也增為1到4倍。本篇論文，我們提出了一個改良過後符合多輸入多輸出正交分頻多工(Multiple-input multiple-output orthogonal frequency-division multiplexing, MIMO OFDM)系統中的128點快速傅利葉轉換處理器(Fast Fourier Transform, FFT)。利用以8為基底(Radix-8)的演算法減少複數乘法器的運算量。使用了多路徑延遲換向器的架構(Multi-path Delay Commutator, MDC)增加資料總體傳輸率(Throughput Rate)；也結合了單路徑延遲回朔(Single-path Delay Feedback, SDF)的架構減少硬體成本。記憶體的部分，利用存取位址做改良後，對於複數乘法的時間點做重新安排達到資料共享，使複數乘法器的部分的使用率增加，以減少複數乘法器的個數，因為乘法器在整個傅利葉轉換處理器(FFT)中所佔的面積較大，所以整個快速傅利葉轉換處理器的面積也會明顯下降。
本篇論文利用Tsmc 0.18um製成合成過後模擬正確無誤，整體面積是1691120um2，操作的頻率是40MHz，可以在3.2us內完成快速傅利葉轉換的運算，符合IEEE 802.11n的規範。全部四個平行的快速傅利葉轉換處理器所需要的複數乘法器的面積只相當於3.84個傳統的複數乘法器，面積上有相當的改良。

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