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研究生: 沈君謙
論文名稱: 重複使用區塊層級測試資料於系統層級平行化驗證
Reusing Block-Level Test Patterns for Concurrency-Oriented Verification at System Level
指導教授: 張世杰
口試委員: 張世杰
黃俊達
王俊堯
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 43
中文關鍵詞: 系統單晶片驗證平行重複使用
外文關鍵詞: system-on-chip, verification, concurrency, reuse
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  • 由於系統單晶片設計複雜度日漸提高,系統單晶片內含有各種不同原件之集成,其原件間的複雜互動導致系統單晶片之驗證難度也隨之提高。為了驗證由系統層級原件間互動所導致之系統層級特有錯誤,一般廣泛使用的方法為在一時間觸發多個原件,平行化原件間互動以期能產生資源競爭,進而驗證原件間互動問題。而一般廣泛產生原件間互動之方法為隨機方法,可能難以產生複雜邊界條件,並難以執行特定原件功能。而重複使用區塊層級測試資料將可以達成在系統層級重新產生複雜邊界條件及執行特定原件功能等目標。我們將區塊層級測試資料重新組合排序後應用至系統層級之外,尚提出一平行觸發原件間互動之演算法,加入至多之平行原件間互動。我們將我們的方法應用至Nios SoC,達成驗證各式邊界條件、驗證各式特定功能、及產生大量平行原件間互動的目標。


    Chapter 1 INTRODUCTION Chapter 2 INTERACTION MODEL Chapter 3 CONSTRUCTION OF A BASIC INTERACTION ARRANGEMENT GRAPH Chapter 4 INSERTION OF CONCURRENT INTERACTIONS Chapter 5 DERIVATION OF INTERACTION ARRANGEMENT GRAPH FOR MULTIPLE COMPONENTS Chapter 6 EXPERIMENTAL RESULTS Chapter 7 CONCLUSIONS

    REFERENCES
    [1] Alper Sen, “Concurrency-oriented verification and coverage of system-level designs,” ACM Transactions on Design Automation of Electronic Systems, 2011.
    [2] Altera Inc., “Nios II hardware development tutorial,” San Jose, CA, 2011.
    [3] Azeddien M. Sllame and Vladimir Drabek, “An efficient list-based scheduling algorithm for high-level synthesis,” in Proc. of the Euromicro Symposium on Digital Systems Design, 2002.
    [4] Adriel Cheng, Cheng-Chew Lim, and Atanas Parashkevov, “A software test program generator for verifying system-on-chip,” in Proc. of 10th IEEE International High Level Design Validation and Test Workshop 2005.
    [5] Collett International Research Inc., “2002 IC/ASIC functional verification Study,” 2002.
    [6] EDAptive Computing Inc., “VectorGenTM: automated test vector generation.”
    [7] Edmonds Jack, “Paths, trees, and flowers,” in Canadian Journal of Mathematics, 1965.
    [8] F. Hunsinger, S. Francois, and A. A. Jerraya, “Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip,” in Proc. of 4th International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions, 2003.
    [9] Guy Mosensoson, “Practical approaches to SoC verification,” in Proc. of DATE User Forum, 2002.
    [10] Janick Bergeron, Eduard Cerny, Alan Hunter, and Andy Nightingale, “Verification mathodolagy manual for SystemVerilog,” 2005.
    [11] Kolmogorov Vladimir, “Blossom V: a new implementation of a minimum cost perfect matching algorithm,” Mathematical Programming Computation, 2009.
    [12] Xiaoxi Xu and Cheng-Chew Lim, “Using transfer-resource graph for software-based verification of system-on-chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008.

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