當漏電功率成為總電功率的主要貢獻者，電源閘控已經變成一個最有效減少漏電功率技術。在本論文中，我們提出三個重要針對電源閘控最佳化的設計問題。第一個針對電源閘控重要問題是在喚醒過程時要限制浪湧電流，一般來說，喚醒排程是用來控制打開睡眠電晶體的時間。我們提出一個新的喚醒排程規劃，考慮喚醒時間與硬體資源之間的關係。第二個重要問題是在一個先進電源閘控的設計上，其需要被打開的組件個數與其位置都是隨著當時的工作在動態的改變。因此，一個重要的問題就是針對組件層級上電源閘控設計喚醒排程。就我們所知，這是第一個深入的研究於針對高速架構上電源閘控設計的及時組件層級喚醒排程。最後一個重要問題，因為睡眠電晶體在工作時都一直連續的打開，負偏壓溫度不穩定性影響睡眠電晶體的生命可靠度，會導致整個電源閘控電路的效能降低，我們提出一個新穎的負偏壓溫度不穩定性導向電源閘控架構來延長睡眠電晶體的生命時間。

As leakage power has become a major contributor to the total power consumption, power gating has been a very effective method among leakage reduction techniques. In this dissertation, we propose three important design issues for optimization of power gating design. One important design issue for a power gating design is to limit the surge current during the wakeup process. Normally, a wakeup scheduling which is required to control turn-on times of sleep transistors should be well-designed. We propose a new wakeup scheduling formulation which considers the trade-off between wakeup times and hardware resources. Second, for a modern power gating design, the number of modules that need to be turned on and their locations may vary depending on the task to be performed at runtime. Accordingly, the important issue is the wakeup scheduling for the module-level power gating design. To the best of our knowledge, this is the first in-depth study on on-line module-level wakeup scheduling for high-performance architectures. Last, since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI) influences the lifetime reliability of PMOS sleep transistors seriously which leads to the performance degradation of the power gating design. We present a novel NBTI-aware power gating architecture to extend the lifetime of PMOS sleep transistors.

[1] A. Abdollahi, F. Fallah and M. Pedram, “A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design,” IEEE Transactions on VLSI Systems, vol. 15, no. 1, January 2007, Page(s): 80 - 89.
[2] H. Abrishami, S. Hatami, B. Amelifard, M. Pedram, “NBTI-Aware Flip-Flop Characterization and Design,” Proc. of the GLSVLSI, pp. 29-34, 2008.
[3] P. E. Allen and D. R. Hoberg, CMOS Analog Circuit Design, Oxford University press. NY, pp.323-362.
[4] D. Brelaz, “New Methods to Color the Vertices of a Graph,” Communications of the ACM, Vol.22, Issue 4, Apr. 1979.
[5] C. Bron and J. Kerbosch, “Algorithm 457: Finding All Cliques of an Undirected Graph,” Communications of the ACM, Vol. 16, Issue 9, 1973.
[6] A. Calimera, E. Macii, and M. Poncino, “NBTI-Aware Sleep Transistor Design for Reliable Power-Gating,” Proc. of the GLSVLSI, pp. 333-338, 2009.
[7] A. Calimera, E. Macii, and M. Poncino, “NBTI-aware Power Gating for Concurrent Leakage and Aging Optimization,” Proc. of the ISLPED, pp. 127-132, 2009.
[8] G. Chen, K. Y. Chuah, M. F. Li, Daniel SH Chan, C. H. Ang, J. Z. Zheng, Y. Jin and D. L. Kwong,” Dymanic NBTI of PMOS Transistors and Its Impaction on Device Lifetime,” Proc. of the AIRPS, pp. 196-202, 2003.
[9] S. H. Chen and J. Y. Lin, “Experiences of low power design implementation and verification,” Prof. of the ASPDAC, pp. 742-747, 2008.
[10] Y. T. Chen, D. C. Juan, M. C. Lee, and S. C. Chang, “An Efficient Wakeup Schedule during Power Mode Transition Considering Spurious Glitches Phenomenon,” Proc. of the ICCAD, pp. 779-782, 2007.
[11] D.S. Chiou, D.C. Juan, Y.T. Chen, and S.C. Chang, ”Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization,” Proc. of the DAC, pp. 81-86, 2007.
[12] A.H. Farrahi, D.J. Hathaway, M. Wang, M. Sarrafzadeh, “Quality of EDA CAD tools: definitions, metrics and directions,” Proc. of the ISQED, pp. 395 – 405, 2000.
[13] S. Hong and H. Kim, “An Integrated GPU Power and Performance Model,” Proc. of ISCA, pp. 280-289, 2010.
[14] H. Jiang, M. Marek-Sadowska and S. R. Nassif, “Benefits and Costs of Power-Gating Technique,” Proc. of the ICCD, pp. 559-566, 2005.
[15] H. Jiang and M. Marek-Sadowska, “Power Gating Scheduling for Power/Ground Noise Reduction,” Proc. of the DAC, pp.980-985, 2008.
[16] R. Joseph, D. Brooks, M. Martonosi, “Control Techniques to Eliminate Voltage Emergencies in High Performance Processors,” Proc. of HPCA, pp. 79-90, 2003.
[17] D.C. Juan, Y.T. Chen, M.C. Lee, S.C. Chang, "An Efficient Wakeup Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs," IEEE Transactions on VLSI Systems, vol. 18 , Issue: 2, Feb. 2010, Page(s): 246 - 255.
[18] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design, Springer, Inc, 2007.
[19] S. Kim, S. V. Kosonocky and D. R. Knebel, “Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures,” Proc. of the ISLPED, pp. 22-25, August 25-27, 2003.
[20] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “An Analytical Model for Negative Bias Temperature Instability,” Proc. of the ICCAD, pp. 493-496, 2006.
[21] Y. Lee, D-K Jeong, and T. Kim, “Simultaneous Control of Power/Ground Current, Wakeup Time and Transistor Overhead in Power Gated Circuits,” Proc. of the ICCAD, pp. 169-172, 2008.
[22] M. C. Lee, Y. T. Chen, Y. T. Cheng, and S. C. Chang, “An Efficient Wakeup Scheduling Considering Resource Constraint for Sensor-Based Power Gating Designs,” Proc. of the ICCAD, pp. 457-460, 2009.
[23] F. Li and L. He, “Maximum Current Estimation Considering Power Gating,” Proc. of the ISPD, pp. 106-111, April 1-4, 2001.
[24] C. Long and L. He, “Distributed Sleep Transistor Network for Power Reduction,” IEEE Transaction on VLSI systems, vol. 12, no. 9, pp. 937-946, 2004.
[25] Y. Lu, L. Shang, H. Zhou, H. Zhu, F. Yang, and X. Zeng, “Statistical Reliability Analysis under Process Variation and Aging Effects,” Proc. of the DAC, pp. 514-519, 2009.
[26] H. Luo, Y. Wang, R. Luo, H. Yang, and Y. Xie, “Temperature-Aware NBTI Modeling Techniques in Digital Circuits,” IEICE Transactions Electron, vol. E92 – C, pp. 875-886, 2009.
[27] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,” IEEE Electron Device Letters, vol. 26, issue 8, pp. 560-562, 2005.
[28] A. Ramalingam, A. Devgan and D. Z. Pan, “Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce,” Journal of Low Power Electronics, vol.3, pp. 1-8, 2007.
[29] T. Sato, A. Inoue, T. Shiota, T. Inoue, Y. Kawabe, T. Hashimoto, T. Imamura, Y. Murasaka, M. Nagata, and A. Iwata, "On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications," pp. 290-603, Proc. of the ISSCC, 2007.
[30] D. K. Schroder, and J. A. Babcock, “Negative Bias Temperature Instability: Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing,” Joural of Applied Physics, vol. 94, no. 1, 2003.
[31] A. S. Sendra and K. C. Smith, Microelectronic Circuits - Fourth Edition, Oxford University Press, 1998.
[32] K. Shi, and D. Howard, “Challenges in Sleep Transistor Design and Implementation in Low-Power Designs,” Proc. of the DAC, pp. 113-116, July 24-28, 2006.
[33] W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The Impact of NBTI on the Performance of Combinational and Sequential Circuits,” Proc. of the DAC, pp. 364-369, 2007.
[34] H. Xu, R. Vemuri, W.-B. Jone, “Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs,” Proc. of the ICCAD, pp. 637–641, 2010.
[35] Y. Xu, W. Liu, Y. Wang, J. Xu, X. Chen, H. Yang, "On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise," Proc. of the ISVLSI, pp.109-114, 2009.
[36] H. I Yang, C. T. Chuang, and W. Hwang, “Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-gate Devices,” Proc. of the ISCAS, pp. 377-380, 2007.
[37] X. Yang, and K. Saluja, “Combating NBTI Degradation via Gate Sizing,” Proc. of the ISQED, pp. 47-52, 2007.
[38] http://www.legitreviews.com/article/1228/12/
[39] Synosys Inc. HSPICE® User Guide: Simulation and Analysis, Version-C 2009. 09, Sep. 2009.