研究生: |
朱家佑 Chu, Chia-Yu |
---|---|
論文名稱: |
一個使用40奈米製程之具有低刷新功率的邏輯相容2T增益單元內嵌式動態隨機存取記憶體 A Logic-Compatible 2T Gain-Cell Embedded DRAM Featuring Low Refresh Power in 40-nm Logic Process Technology |
指導教授: |
謝秉璇
Hsieh, Ping-Hsuan |
口試委員: |
謝志成
Hsieh, Chih-Cheng 廖育德 Liao, Yu-Te |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2024 |
畢業學年度: | 112 |
語文別: | 英文 |
論文頁數: | 79 |
中文關鍵詞: | 內嵌式記憶體 、動態隨機存取記憶體 、增益單元 、資料保留時間 、低刷新功率 |
外文關鍵詞: | Embedded memory, DRAM, Gain cell, Data retention time, Low refresh power |
相關次數: | 點閱:2 下載:0 |
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近年來,內嵌式動態隨機存取記憶體由於其高密度和低漏電功耗而成為SRAM的新興替代記憶體。然而,傳統的一個電晶體及一個電容組成的內嵌式動態隨機存取記憶體需要特殊的製程步驟來打造單元電容,既複雜又昂貴。此外,破壞性讀取操作的特性使其需要在讀取後立即進行回寫機制。這會造成更高的功耗和較低的記憶體陣列可用性。因此,為了解決上述問題,增益單元內嵌式動態隨機存取記憶體因其高密度、低漏電功耗以及與系統單晶片完全邏輯兼容而成為有發展性的內嵌式記憶體。然而,先進製程中嚴重的漏電流會使增益單元中儲存資料的電壓惡化,並大幅減少增益單元內嵌式動態隨機存取記憶體的資料保留時間,從而導致頻繁的刷新操作和更高的刷新功率。因此,先進的CMOS製程中,延長資料保留時間仍然具有挑戰性。在這篇論文中,我們提出了一個採
用40奈米製程之一千位元的增益單元內嵌式動態隨機存取記憶體。其儲存單元面積為0.52微米平方,並透過採用輸入輸出電晶體作為寫入電晶體、金屬層繪製的叉指儲存電容、提升資料「0」的寫入電壓以及複製讀出單元來實現低刷新功率和高操作頻率。此外,所提出的增益單元也解決了先前論文中出現的問題,包括讀出位元線飽和以及電荷注入等。量測結果顯示電源電壓的操作範圍為0.7伏特至1.1伏特。在額定操作電壓0.9伏特之下,資料保留時間為21微秒、操作頻率為7億赫茲、每百萬個位元的刷新功率為2.96毫瓦。
In recent years, Embedded DRAM(eDRAM) has become an emerging alternative for SRAM due to its high-density and low-leakage power. However, conventional 1T1C eDRAM requires dedicated process steps to fabricate the cell capacitor, which is complicated and expensive. In addition, it suffers from destructive read operation, which needs write-back mechanism immediately after read operation. This results
in higher power consumption and lower memory array availability. Therefore, to address the above issues, Gain-cell embedded DRAM(GC-eDRAM) becomes a popular alternative for embedded memory due to its high-density, low-leakage power, and fully logic-compatible for system-on-chip(SoC) design. Nonetheless, the severe leakage current in advanced technology node will deteriorate the voltage of stored data in a gain cell and substantially decrease the data retention time of GC-eDRAM, which leads to frequent refresh operation and higher refresh power. Consequently, it is still challenging to prolong data retention time in scaled CMOS technology.
In this thesis, we propose a 1kb 2T GC-eDRAM in 40-nm technology, with
a unit area of 0.52μm2, achieves low refresh power and high operating frequency by adopting I/O PMOS as write transistor, interdigitated storage capacitor drawn with metal layer, higher voltage level for writing data’0’ and replica readout cell.
Besides, the proposed 2T gain cell also addresses issues presented in the previous 2T configuration such as RBL saturation and charge injection.
The measurement result shows the operating range of supply voltage is from 0.7V to 1.1V with 21μs data retention time, 700MHz operating frequency and 2.96mW/Mb refresh power under 0.9-V nominal power supply.
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