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研究生： 李志忠
Chih-Chung Li
論文名稱： 可用於單一輸入輸出/多重輸入輸出通訊系統之基頻通道仿真器
A Baseband Channel Emulator for SISO/MIMO Communications
指導教授： 馬席彬博士
Prof. Hsi-Pin Ma
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 中文
論文頁數： 88
中文關鍵詞： 無線通道 、通道仿真器 、多重輸入輸出 、通道模型 、多路徑效應 、雷利衰減 、路徑耗損 、頻率漂移 、時脈漂移 、白色高斯雜訊
外文關鍵詞： Wireless Channel, Channel Emulator, MIMO, Channel Model, Multi-path Effect, Rayleigh Fading, Path Loss, Frequency Offset, Timing Offset, AWGN
相關次數： 點閱：2  下載：0 
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    • 近年來，由於無線通訊系統的理論與技術快速的發展，投入研究的課題也多方面的發展。其中又以無線通訊機中的基頻電路設計為最，成為熱門的研究課題。在設計無線通訊基頻電路的過程中，無線通道對於系統的影響是非常重要的因素。過去常使用的通道模擬方式大多為軟體的無線通道模擬，使用軟體模擬無線通道的缺點為耗時過長，但擁有較高的程式設計彈性，易於改變以適用於其他系統。另一種無線通道模擬的方式是使用無線通道仿真器，此種硬體無線通道模擬的優點在於所需之模擬時間較短，但其可應用性被其硬體所限制。
    在此篇碩士論文中，我們提出一個多功能的無線通道仿真器並加以實作。首先建立一個此無線通道模型，此無線通道模型除了可模擬無線通道中的通道效應外(如多路徑效應、路徑損失等)，還可模擬傳送接收機中硬體的不完美效應(如白色高思雜訊等)。此外，更藉著導入了多輸入輸出(MIMO)天線的通道效應模型，使此模型可用於模擬多天線通訊系統。最後在建立此無線通道模型後，我們將此無線通道仿真器實現於FPGA 實驗版。
    在硬體電路實現的部份，我們採用了許多演算法來做電路化簡，並重複利用不同元件中的類似電路來降低電路面積。使無線通模擬更為便利，不需使用昂貴的儀器或大面積電路。此外，利用本論文所提出的無線通道仿真器，更可改善無線通道仿真器的可應用範圍不廣的缺點，並能適用於大部分目前已知的無線通訊技術。

    Recently, for the development of wireless communication system is getting faster.
    One of the most popular topics in this field is the design of baseband circuit. In the
    progress of developing the baseband circuit, wireless channel effect is very important.
    In the past, software simulation is used to emulate the wireless channel effect. Use
    software simulation is time cost, but it has flexibility with the code. It can also
    changed to suitable for another system easily. Another emulation method is to use the
    hardware channel emulator. Use channel emulator can shorter the simulation time. In
    other words, it has disadvantage of less flexibility.
    In my thesis, a versatile structure baseband channel emulator and then
    implementation. First we construct a baseband channel model. In addition to simulate
    the wireless channel effect (ex. Multi-path Effect, Path Loss), it can also simulate the
    hardware imperfect property of transceiver circuit (ex. AWGN). By adding the
    MIMO channel effect to the channel model, the proposed channel emulator can also
    emulate the multi-antenna communication systems. Finally we implement our channel
    emulator with FPGA development board.
    In hardware implementation, many algorithms are use to simplify the complexity
    of circuit. And then we use the commonly used element to reduce the area of circuit.
    It makes the simulation with channel emulator more easily. By using the proposed
    channel emulator can also improve the disadvantage of application range and then
    use to emulate almost all the wireless communication channel.

    1 Introduction 1 1.1 Wireless Channel Overview 1 1.2 Motivation 2 1.3 Organization of the Thesis 2 2 Baseband Channel Model 3 2.1 SISO Channel Model 3 2.1.1 Multipath Effect 4 2.1.2 Small Scale Fading 6 2.1.2.1 Frequency Selective / Non-Selective Fading 8 2.1.2.2 Rayleigh Fading 11 2.1.2.3 Ricean Fading 12 2.1.2.4 Jakes Model 13 2.1.2.5 Modified Jakes Model 14 2.1.2.6 Frequency Selective Fading 16 2.1.3 Doppler Effect 17 2.1.4 Slow Fading / Fast Fading 19 2.1.5 Large Scale Fading 22 2.1.6 Frequency Offset 25 2.1.7 I/Q imbalance 26 2.1.8 AWGN 28 2.1.9 Sampling Clock Offset 31 II 2.2 MIMO Channel Model 33 2.2.1 Cluster-based Channel Model 37 2.2.2 Break-point Path loss 39 2.2.3 Correlation 40 3 Baseband Channel Emulator 42 3.1 Overview 42 3.2 Architecture Design 42 3.2.1 Multi-path 43 3.2.2 Small-scale Fading 45 3.2.3 Large-scale Fading 45 3.2.4 Frequency Offset 47 3.2.5 I/Q Imbalance 47 3.2.6 AWGN 48 3.2.7 Sampling Clock Offset 48 3.2.8 Correlation 49 3.2.9 SISO Channel Emulator 50 3.2.10 MIMO Channel Emulator 52 4 Functional Simulation Results 53 4.1 Multipath and Delay Spread 53 4.2 Rayleigh Fading and Ricean Fading 54 4.3 Doppler Effect 55 4.4 Propagation Power Loss and Shadowing 56 4.5 Frequency Offset 59 4.6 I/Q Imbalance 59 4.7 AWGN 60 4.8 Sampling Clock Offset 62 III 5 FPGA Prototyping and Measurement 63 5.1 Architecture Optimization 63 5.1.1 Optimization of Less-used Elements 63 5.1.2 Optimization of sin/cos ROM 65 5.2 Word-Length Determination 66 5.3 FPGA Measurement 76 6 Discussions and Conclusions 81 6.1 Commercial Product Comparison 81 6.2 Future Work 82 6.3 Conclusion 83 Bibliography 85

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