為了要符合具備輕、薄、高可靠度以及高解析度主動式液晶顯示器之需求，我們使用循序性側向雷射結晶技術以及氧化矽-氮化矽-氧化矽閘極介電層堆疊結構，在玻璃基板上，製作低溫複晶矽薄膜電晶體，結果顯示其元件性能及可靠度特性都較傳統單層氧化層的薄膜電晶體佳。多層閘極結構薄膜電晶體可以應用在整合周邊驅動電路於低溫複晶矽薄膜電晶體液晶顯示面板上。
本論文，首度提出具有電場增強的尖端結構之嵌入式金屬-氧化矽-氮化矽-氧化矽-複晶矽(MONOS) 非揮發性記憶體，此記憶體元件的製造完全相容於低溫複晶矽製程技術，也不需要額外的製程步驟。藉由適當的光罩設計以及雷射結晶對準的製程技術，可以精確地控制複晶矽晶界在薄膜電晶體通道中的位置。嵌入式非揮發性記憶體不僅可以整合於低溫複晶矽顯示器的每一個畫素內，用以降低功率消耗，而且也可以做為可程式邏輯陣列的應用，擴展可攜式電子裝置額外的附加功能。
MONOS 記憶體可藉由通道熱電子注入以及能帶對能帶穿隧引發熱電洞注入來完成寫入與抹除的操作。經由多次的寫入/抹除循環操作後，記憶體元件顯示出具有良好的耐久性與資料保存能力以及很好的抗寫入/讀取干擾的能力。
此外，MONOS 非揮發性記憶體可以排列組合成NOR 型及NAND型記憶體元件陣列以提供嵌入式可程式邏輯陣列在系統整合面板上一個高度可行的解決方案。研究結果顯示，這些記憶體元件陣列可在低電壓操作下，具有良好的重複寫入/抹除之可靠度及資料保存之能力。

To meet the requirements of active matrix liquid crystal display (AMLCD) with a compact, highly reliable, and high resolution, low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) using sequential lateral solidify (SLS) crystallization technology on a glass substrate are proposed and demonstrated. LTPS-TFTs with oxide–nitride–oxide (ONO) stacked gate structure revealed superior device performance and device reliability characteristics than conventional SiO2 TFTs. This multi stacked layer gate structure capable of sustaining high-voltage operations can greatly enhance the feasibility of implementing LTPS TFTs embedded peripheral in AMLCDs panels.
An embedded MONOS-type memory device with a field-enhancing tip structure with 1-T per cell realized using SLS-LTPS technology is demonstrated for the first time. The memory device fabrication is fully compatible with conventional LTPS processing and the position of Si protrusions can be well-controlled by the SLS alignment technique. Without additional processing steps, this memory cell can be implemented simply by a typical LTPS technology. The embedded NVM can not only be integrated into each pixel to reduce the power consumption of LCD panels, but also act as programmable logic arrays to extend the functionality on portable electronic devices.
Program and erase operations of these MONOS TFTs can be achieved by channel hot electron injection and band-to-band tunneling induced hot hole injection, respectively. These memory cells exhibit fairly good cycling endurance and data retention characteristics, as well as good immunity to program/read disturbance.
The proposed poly-Si TFT MONOS nonvolatile memory could be arranged in a NOR-type array and/or NAND-type array to provide a highly feasible solution for embedded programmable logics arrays on panel systems. Experimental results reveal that these memory arrays can be operated under low-voltage with good reliability in cycling stability as well as data retention capability.

Chapter 1
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Chapter 2
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[2.25] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, Sze, S. M., C. Y. Chang and C. H. Lien, “A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory“, IEEE Electron Device Lett., vol. 28, pp. 809, 2007
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Chapter 3
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Chapter 4
[4.1] Robert S. Sposili and James S. Im, “Sequential lateral solidification of thin silicon films on SiO2”, Appl. Phys. Lett., vol. 69, pp. 2864, 1996
[4.2] C. A. Dimitriadis, M. Kimura, M. Miyasaka, S. Inoue, F. V. Farmakis, J. Brini and G. Kamarinos, “Effect of grain boundaries on hot-carrier induced degradation in large grain polysilicon thin-film transistors ”, Solid-State Electronics, pp. 2045, 2000

Chapter 5
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