研究生: |
何怡瑩 Ho, I-Ying |
---|---|
論文名稱: |
具銦鈍化層的硒化銦電晶體之動態缺陷強化電滯迴圈效應在記憶體應用的研究 Dynamic-trap enhanced hysteresis loops for memory applications using Indium passivated InSe FETs |
指導教授: |
連振炘
Lien, Chen-Hsin |
口試委員: |
施君興
Shih, Chun-Hsin 林彥甫 Lin, Yen-Fu |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 60 |
中文關鍵詞: | 二維材料 、硒化銦 、非揮發性記憶體 、接觸電阻 、遲滯現象 |
外文關鍵詞: | Two-dimensional materials, Indium Selenium, Non-volatile memory, contact resistance, Hysteresis |
相關次數: | 點閱:1 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著半導體技術蓬勃發展,電子產品尺寸日漸縮小,效能卻能增加,這全都有賴於「摩爾定律」。然而,在傳統半導體架構中,元件的微縮已將近物理極限,眼看摩爾定律的發展遇到瓶頸,因此,許多科學家致力於研發新的方法,其中,二維材料就是一個強而有力的候選之一,他擁有次奈米等級的厚度,以及獨特的電性、光學特性,使得二維材料成為運用於次世代電晶體的理想材料,可直接與矽競爭。
本論文主要藉由沉積銦(In)當摻雜層的層狀硒化銦(InSe)場效應晶體(FET)使得電子遷移率在室溫下可高達3700〖cm〗^2 V^(-1) s^(-1),並且在一個月後還能夠保有60%的電子遷移率。此外,由於沉積銦在硒化銦和金電極中間,也改善了接觸電阻,這和低頻雜訊分析結果一致。然而,由於InSe對於氧的反應非常敏感,將元件放在大氣下,並且給定閘極電壓,InSe的表面產生氧化層,而氧化層與InSe之間存在缺陷使得載子被捕捉,造成電滯現象,基於此電滯現象,我們將它運用做為非揮發性記憶體,不像傳統非揮發性記憶體需要繁雜的氧化層製程,就能達到相同的記憶體特性。沉積銦當摻雜層的層狀硒化銦場效應晶體展現了高電子遷移率、高電流開關比、相當大的遲滯窗口、穩定的儲存時間,提供了一個可靠的方法使用二維材料做成記憶體元件。
With the rapid development of semiconductor technology, the size of electronic products scale down but efficiency can be increased, all of which depend on "Moore's Law." However, in the traditional semiconductor architecture, the shrinkage of devices has approached the physical limit, and the development of Moore's Law has encountered bottlenecks. Therefore, many scientists are working on developing new path. Among them, two-diementional materials is one of the strong candidates. They have sub-nano-grade thickness, as well as unique electrical and optical properties, making two-dimensional materials an ideal material for the next generation of transistors, which can compete directly with silicon.
A layered indium selenide (InSe) field‐effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The electron mobility can be as high as 3700〖cm〗^2 V^(-1) s^(-1) at room temperature, and can be retained with 60% after one month. In addition, since the deposited indium is between the indium selenide and Au electrodes, the contact resistance is also improved, which is consistent with the low frequency noise analysis result. However, since InSe is very sensitive to oxygen, when the device is placed under air, then given the gate voltage, the surface of the InSe and the doped indium structure become InO_x, causing an oxide layer on the surface. There are defects on the interface of the oxide layer and InSe, which cause the carrier be captured, resulting in hysteresis. Based on the hysteresis, we use it as a non-volatile memory. Unlike traditional non-volatile memory, which requires a complicated oxide layer process, but the same memory characteristics can be achieved. A layered indium selenide field effect transistor by depositing an indium doping layer exhibits high electron mobility, 〖10〗^5 on/off ratio, large hysteresis window, stable retention, and provides a reliable path to utilize two-dimensional materials to memory device.
[1] Wikipedia, "Moore's Law," from https://en.wikipedia.org/wiki/Moore%27s_law, 2011.
[2] K. Uchida and S.-i. Takagi, "Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors," Applied Physics Letters, vol. 82, no. 17, pp. 2916-2918, 2003.
[3] S. Thiele, W. Kinberger, R. Granzner, G. Fiori, and F. Schwierz, "The prospects of transition metal dichalcogenides for ultimately scaled CMOS," Solid-State Electronics, vol. 143, pp. 2-9, 2018.
[4] A. Dmitriev, V. Vishnjak, G. Lashkarev, V. Karbovskyi, Z. Kovaljuk, and A. Bahtinov, "Investigation of the morphology of the van der Waals surface of the InSe single crystal," Physics of the Solid State, vol. 53, no. 3, pp. 622-633, 2011.
[5] D. A. Bandurin et al., "High electron mobility, quantum Hall effect and anomalous optical response in atomically thin InSe," Nature nanotechnology, vol. 12, no. 3, p. 223, 2017.
[6] C. Sun, H. Xiang, B. Xu, Y. Xia, J. Yin, and Z. Liu, "Ab initio study of carrier mobility of few-layer InSe," Applied Physics Express, vol. 9, no. 3, p. 035203, 2016.
[7] P.-H. Ho et al., "High-mobility InSe transistors: the role of surface oxides," Acs Nano, vol. 11, no. 7, pp. 7362-7370, 2017.
[8] S.-L. Li et al., "Thickness-dependent interfacial coulomb scattering in atomically thin field-effect transistors," Nano letters, vol. 13, no. 8, pp. 3546-3552, 2013.
[9] X. Wang, J. B. Xu, C. Wang, J. Du, and W. Xie, "High‐Performance Graphene Devices on SiO2/Si Substrate Modified by Highly Ordered Self‐Assembled Monolayers," Advanced Materials, vol. 23, no. 21, pp. 2464-2468, 2011.
[10] S. Ghatak, A. N. Pal, and A. Ghosh, "Nature of electronic states in atomically thin MoS2 field-effect transistors," Acs Nano, vol. 5, no. 10, pp. 7707-7712, 2011.
[11] B. Radisavljevic, A. Radenovic, J. Brivio, i. V. Giacometti, and A. Kis, "Single-layer MoS 2 transistors," Nature nanotechnology, vol. 6, no. 3, p. 147, 2011.
[12] M. Li et al., "High Mobilities in Layered InSe Transistors with Indium‐Encapsulation‐Induced Surface Charge Doping," Advanced Materials, vol. 30, no. 44, p. 1803690, 2018.
[13] H. Jin, J. Li, L. Wan, Y. Dai, Y. Wei, and H. Guo, "Ohmic contact in monolayer InSe-metal interface," 2D Materials, vol. 4, no. 2, p. 025116, 2017.
[14] G. Ghibaudo, “New Method for The Extraction of MOSFET Parameters,” Electronics Letters, vol.24, no. 9, pp. 543-545, 1988.
[15] Y. Xu, T. Minari, K. Tsukagoshi, J. Chroboczek, and G. Ghibaudo, "Direct evaluation of low-field mobility and access resistance in pentacene field-effect transistors," Journal of Applied Physics, vol. 107, no. 11, p. 114507, 2010.
[16] H.-L. Tang et al., "Multilayer graphene–WSe2 heterostructures for WSe2 transistors," ACS nano, vol. 11, no. 12, pp. 12817-12823, 2017.
[17] S. Bertolazzi, D. Krasnozhon, and A. Kis, "Nonvolatile memory cells based on MoS2/graphene heterostructures," ACS nano, vol. 7, no. 4, pp. 3246-3252, 2013.
[18] M. S. Choi et al., "Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices," Nature communications, vol. 4, p. 1624, 2013.
[19] D. Li, X. Wang, Q. Zhang, L. Zou, X. Xu, and Z. Zhang, "Nonvolatile floating‐gate memories based on stacked black phosphorus–boron nitride–MoS2 heterostructures," Advanced Functional Materials, vol. 25, no. 47, pp. 7360-7365, 2015.
[20] E. Zhang et al., "Tunable charge-trap memory based on few-layer MoS2," ACS nano, vol. 9, no. 1, pp. 612-619, 2014.
[21] Q. Feng, F. Yan, W. Luo, and K. Wang, "Charge trap memory based on few-layer black phosphorus," Nanoscale, vol. 8, no. 5, pp. 2686-2692, 2016.
[22] J. B. Johnson, "Thermal agitation of electricity in conductors," Physical review, vol. 32, no. 1, p. 97, 1928.
[23] H. Nyquist, "Thermal agitation of electric charge in conductors," Physical review, vol. 32, no. 1, p. 110, 1928.
[24] Von Haartman, M., et al., Low-frequency noise in advanced MOS devices. 2007, Springer Science & Business Media.
[25] A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE journal of solid-state circuits, vol. 33, no. 2, pp. 179-194, 1998.
[26] K. H. Lundberg, "Noise sources in bulk CMOS," Unpublished paper, vol. 3, p. 28, 2002.
[27] D. Rigaud, M. Valenza, and J. Rhayem, "Low frequency noise in thin film transistors," IEE Proceedings-Circuits, Devices and Systems, vol. 149, no. 1, pp. 75-82, 2002.
[28] R. Hettiarachchi, T. Matsuki, W. Feng, K. Yamada, and K. Ohmori, "Behavior of Low-Frequency Noise in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors for Different Impurity Concentrations," Japanese Journal of Applied Physics, vol. 50, no. 10S, p. 10PB04, 2011.
[29] N. Arpatzanis, A. Tsormpatzoglou, C. Dimitriadis, K. Zekentes, N. Camara, and M. Godlewski, "Electrical and low frequency noise properties of 4H‐SiC p+–n–n+ junction diodes," physica status solidi (a), vol. 203, no. 10, pp. 2551-2557, 2006.
[30] Yamamoto, Y., Technological Innovation of Thin-Film Transistors: Technology Development, History,and Future, in Japanese Journal of Applied Physics. 2012.
[31] Franklin, A.D., DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications, in Science. 2015. p. aab2750.
[32] S. Christensson, I. Lundström, and C. Svensson, "Low frequency noise in MOS transistors—I theory," Solid-State Electronics, vol. 11, no. 9, pp. 797-812, 1968.
[33] P. Dutta and P. Horn, "Low-frequency fluctuations in solids: 1 f noise," Reviews of Modern physics, vol. 53, no. 3, p. 497, 1981.
[34] Tickle, A.C., Thin-film transistors: a new approach to microelectronics. 1969, John Wiley & Sons.
[35] M. Agu, "1/f fluctuations in diffusion processes of effective space dimension less than one," Journal of Applied Physics, vol. 54, no. 3, pp. 1190-1192, 1983.
[36] G. Ghibaudo, O. Roux, and J. Brini, "Modeling of contuctance fluctuations in small area metal–oxide–semiconductor transistors," physica status solidi (a), vol. 127, no. 1, pp. 281-294, 1991.
[37] Von Haartman, M., et al., Low-frequency noise in advanced MOS devices. 2007, Springer Science & Business Media.
[38] F. Hooge, "1/f noise," Physica B+ C, vol. 83, no. 1, pp. 14-23, 1976.
[39] Hooge, F., et al., Lattice scattering causes 1/ƒ noise, in Physics Letters A. 1978. p. 315-316.
[40] I. Hafez, G. Ghibaudo, and F. Balestra, "A study of flicker noise in MOS transistors operated at room and liquid helium temperatures," Solid-state electronics, vol. 33, no. 12, pp. 1525-1529, 1990.
[41] G. Ghibaudo, O. Roux, C. Nguyen‐Duc, F. Balestra, and J. Brini, "Improved analysis of low frequency noise in field‐effect MOS transistors," physica status solidi (a), vol. 124, no. 2, pp. 571-581, 1991.
[42] T.-C. Fung, G. Baek, and J. Kanicki, "Low frequency noise in long channel amorphous In–Ga–Zn–O thin film transistors," Journal of Applied Physics, vol. 108, no. 7, p. 074518, 2010.
[43] C. H. Ho and Y. J. Chu, "Bending photoluminescence and surface photovoltaic effect on multilayer InSe 2D microplate crystals," Advanced Optical Materials, vol. 3, no. 12, pp. 1750-1758, 2015.
[44] M. Chen, H. Nam, S. Wi, G. Priessnitz, I. M. Gunawan, and X. Liang, "Multibit data storage states formed in plasma-treated MoS2 transistors," Acs Nano, vol. 8, no. 4, pp. 4023-4032, 2014.
[45] A. T. Neal, R. Pachter, and S. Mou, "P-type conduction in two-dimensional MoS2 via oxygen incorporation," Applied Physics Letters, vol. 110, no. 19, p. 193103, 2017.
[46] T. Nishi, K. Kanai, Y. Ouchi, M. R. Willis, and K. Seki, "Oxygen effects on the interfacial electronic structure of titanyl phthalocyanine film: p-Type doping, band bending and Fermi level alignment," Chemical physics, vol. 325, no. 1, pp. 121-128, 2006.F