這篇論文中，我們在覆晶式(flip-chip)封裝(package)的架構下，針對輸出入信號歪斜(I/O signal skew)的考量，提出了一個三階段的設計流程將平面規劃(floorplanning)和凸塊接合點(bump pads)分派予以自動化。在第一階段中，我們使用最小花費暨最大網路流演算法(minimum cost maximum flow)產生初始的凸塊接合分派結果。在第二階段中，我們用分割晶片(partitioned-based)的原則，將所有的平面規劃模組(modules)平均散佈到整個晶片四周。此外我們利用定錨(anchoring)和重新配置(relocation)的技巧有效的配置輸出入信號緩衝器(I/O buffers)。第三階段，我們部分調整凸塊接合點的分派，達到的改善輸出入信號歪斜和總線長(total wirelength)的目的。在每一個階段，我們都考慮到其它階段的限制和目的而以宏觀的角度解決當階段的問題。實驗結果顯示，傳統的平面規劃工具所產生出來的信號歪斜程度是我們的 2% 到 280% 倍。而總線長也會是我們的 100% 以上。而我們在第三階段的部分調整凸塊接合點，還能再進一步的改進以上兩個目標。

In this thesis, we propose a three stage design layout methodology for flip-chip. In stage 1, we use minimum cost flow to produce an initial bumper signal assignment, and then solve the flip-chip floorplanning problem using a partitioned-based technique to spread the modules across the chip. With an anchoring and relocation technique, we can effectively place I/O buffers at suitable locations. Finally, we further reduce signal skew and monotonic routing density by refining the bumper signal assignment. In each stage, we solve the problem in a broader view. Experimental results show that signal skew of traditional
floorplanners range from 2% to 280% higher than ours. And the total wirelength of other floorplanners is asmuch as 100%higher than ours. Moreover, the bumper signal refinement
after floorplanning can further reduce monotonic routing density and signal skew.

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[19] http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview

[20] http://vlsicad.eecs.umich.edu/BK/parquet/

[21] http://cc.ee.ntu.edu.tw/ ywchang/research.html