本篇論文，是以4H-SiC為材料，製作橫向型高崩潰電壓元件，如PiN二極體、LDMOS，並應用深溝槽隔離 (Deep Trench Isolation, DTI)、double RESURF (Reduced Surface Field) 原理與氧化後NO退火製程於元件研製。
在元件設計中，double RESURF的原理，能夠幫助空乏區於漂移區垂直以及水平方向充分展開，因此在提高漂移區濃度以降低導通電阻的同時，能夠維持相同的崩潰電壓。同時，也採取了氧化後NO退火的製程，來進一步改進導通電阻值。
根據量測的結果，PiN二極體最佳特徵導通電阻為1.57 mΩ-cm2，崩潰電壓為975 V；LDMOS最佳特徵導通電阻為133 mΩ-cm2，崩潰電壓為809 V；DTI測試結構可以達成945 V 電路高低壓區域隔離的效果。由上述結果可知，本實驗所製作的PiN、LDMOS元件其BFOM (Baliga's Figure Of Merit) 超過了Si極限，以及那些以Si製作的橫向型元件，再再顯現了SiC橫向型元件優異的發展潛力。

In this study, deep trench isolation (DTI), double reduced surface field (RESURF) concept, and post-oxidation NO annealing were applied to design and fabrication of lateral high voltage devices in 4H-SiC, such as PiN diode and LDMOS.
In the design of the fabricated devices, the concept of double RESURF is employed, which helps depletion of the drift region from both top and bottom sides. As a result, the drift region concentration can be increased with the decrease in on-resistance while keeping the same breakdown voltage. In the meantime, post-oxidation NO annealing is also employed in the process to improve the on-resistance.
According to the measurement results, the best specific on-resistance is 1.57 mΩ-cm2 for PiN diodes and breakdown voltage achieved is 975 V. For LDMOS, the best specific on-resistance is 133 mΩ-cm2 with a breakdown voltage of 809 V. As for DTI test structure, which isolates high side and low side functions of the circuits, can isolate 945 V. Based on these result, the Baliga’s Figure Of Merit (BFOM) of the PiN diode and LDMOS demonstrated in this work has surpassed the Si limit, and exceed those of the Si lateral devices, which shows the excellent potential of SiC lateral devices.

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