以滿足性為基底的路徑延遲錯誤自動測試向量產生器

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研究生：	吳志鴻 Chih-HungWu
論文名稱：	以滿足性為基底的路徑延遲錯誤自動測試向量產生器 A Satisfiability-Based Auto Test Pattern Generation for Path Delay Faults
指導教授：	劉靖家 Jing-Jia Liou
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	47
中文關鍵詞：	測試、延遲、路徑、錯誤、定值錯誤、轉換錯誤
外文關鍵詞：	testing, delay, path, fault, stuck-at fault, transition faults
相關次數：	點閱：2 下載：0
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隨著超大型積體電路的發展，以確保數位系統時間特性正確性為目標的延遲測試變的愈來愈重要，對於在高頻工作中的電路，任何一個細小的製程缺陷都可能引入不正確的延遲，導致它無法在給定的工作頻率下正常工作。而自動測試向量產生器是以產生樣本去測試一個嚴謹的邏輯階層電路的過程。在這一篇論文中，我們針對定值錯誤(stuck-at fault)、轉換錯誤(transition faults)和路徑延遲錯誤(path delay fault)等的延遲錯誤模型(delay fault model)，開發其自動測試向量產生器。在我們的研究及實驗中，我們的自動測試向量產生器是使用滿足性的(SAT)引擎，此引擎在調整(justification)和蘊含(implication)都有很好的效能。
而其中的定值錯誤自動測試向量產生器我們是使用路徑導向的演算法，這個演算法是指當一個錯誤的一條傳輸路徑找不到它的測試向量時，我們就會換另一條路徑找其測試向量。而我們同時也比較了SAT的自動測試向量產生器、亞特蘭大自動測試向量產生器和PODEM-Like自動測試向量產生器。比較結果說明了我們SAT的自動測試向量產生器有著更好的效能。我們使用了功能調整(functional justification)架構了轉換錯誤自動測試向量產生器，轉換錯誤的傳輸路徑是使用和定值錯誤自動測試向量產生器的路徑導向演算法。而路徑延遲錯誤自動測試向量產生器則是針對健全路徑、非健全路徑和功能性敏感路徑來產生其測試向量，我們提出了以SAT為基底的路徑延遲錯誤自動測試向量產生器，並以保留適合條件的方式來減少自動測試向量產生器的複雜度。

We develop a automatic test pattern generator (ATPG) for stuck-at faults, transition faults and path delay faults. Our ATPG is based on a SAT engine. The SAT engine has efficient implementation of justification and implication.
Our stuck-at fault ATPG uses the path-oriented algorithm. The path-oriented algorithm is that when we find a propagation path which can’t propagate the fault, we change another path one by one. We will show the experimental data of our stuck-at fault ATPG compared with
Atalanta ATPG and PODEM-like ATPG. Our stuck-at fault ATPG is more efficient than Atalanta ATPG and PODEM-like ATPG. We implement functional justification tests to transition faults.
The propagation path of transition faults uses the path-oriented algorithm similar to stuck-at fault ATPG. Our path delay fault ATPG generates test patterns for Robust paths, Non-robust paths and Functional Sensitizable paths. We
propose a SAT-based approach of implementing path delay
fault ATPG. It decreases the complexity of ATPG by keeping the constraints information from the last path.

Introduction 7
1 Delay Fault Testing Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PathDelayFaultClassification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 RobustTestablePathDelayFaults . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Non-robustTestablePathDelayFaults . . . . . . . . . . . . . . . . . . . . 9
2.3 FunctionalSensitizablePathDelayFaults . . . . . . . . . . . . . . . . . . 10
3 Satisfiability(SAT)-based Background . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Previous Work of Path Delay Fault ATPG 12
1 OverviewofPreviousPathDelayFaultATPG . . . . . . . . . . . . . . . . . . . . 12
1.1 RobustTests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 High Quality Non-Robust Tests . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 High Quality Functional Sensitizable Tests . . . . . . . . . . . . . . . . . 15
2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SAT-based Framework for Stuck-At Fault ATPG 18
1 OverviewofOurStuck-AtFaultATPG. . . . . . . . . . . . . . . . . . . . . . . . 18
2 The algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 ExperimentalResultsComparison . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Compare to Atalanta ATPG without fault simulation . . . . . . . . . . . . 21
3.2 Compare to Atalanta ATPG and PODEM-like ATPG with fault simulation . 23
SAT-based Framework for Transition Fault ATPG 26
1 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.2 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 The algorithm of Our Transition Fault ATPG . . . . . . . . . . . . . . . . . . . . . 29
3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
The Proposed Method for Path Delay Fault ATPG 33
1 OverviewofOurSAT-basedPathDelayFaultATPG . . . . . . . . . . . . . . . . 33
1.1 PathDelayFaultModel . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Drawbacks ofTheTraditionalPathDelayFaultATPGs . . . . . . . . . . . 33
2 Proposed Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3 An Example to Illustrate The Constraint Reduction for Multiple Paths . . . . . . . 37
4 An Example to Illustrate The Constraint Reduction for Single-path Sensitization . . 42
5 ExperimentalResultsAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Conclusions and Future Work 44
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
List of Tables
1 Values covering the off-input values. . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Off-input constraints for propagating stuck-at fault . . . . . . . . . . . . . . . . . 21
2 The performance of ATPG without fault simulation . . . . . . . . . . . . . . . . . 23
3 The fault efficiency ofAtalantaATPG . . . . . . . . . . . . . . . . . . . . . . . . 23
4 The fault efficiency ofourStuck-atFaultATPG . . . . . . . . . . . . . . . . . . . 24
5 Theperformance ofATPGwithfault simulation . . . . . . . . . . . . . . . . . . . 24
6 The fault efficiency ofATPGwithfault simulation. . . . . . . . . . . . . . . . . . 25
1 Off-input constraints for propagating transition faults . . . . . . . . . . . . . . . . 30
2 Experimental results of our transition fault ATPG . . . . . . . . . . . . . . . . . . 32
1 RobustConstraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2 Non-robustConstraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 FSConstraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4 The experimentaldataofprototypeofourpath delayfaultATPG . . . . . . . . . . 42
5 The experimental data of using the speed-up skill <1> . . . . . . . . . . . . . . . 43
6 The experimental data of using both speed-up skills . . . . . . . . . . . . . . . . . 43
List of Figures
1 Blockof test scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Timingof test scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Coveringrelations in thefive-valuedlogic system . . . . . . . . . . . . . . . . . . 13
2 ExampleofFSpath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1 ExampleCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Theflowchart ofSAT-basedStuck-atFaultATPG . . . . . . . . . . . . . . . . . . 22
1 Model for sequential circuits (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Model for sequential circuits (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Functional justificationtestingscheme . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Our transition fault ATPG flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 31
1 The circuit ofC17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2 The states of on-input and off-inpt of the first path for generating robust test pattern 39
3 The representation numbers of all wires in the circuit C17 for Zchaff solver . . . . 39
4 Testpattern verificationof thefirst path . . . . . . . . . . . . . . . . . . . . . . . 40
5 The states of on-input and off-inpt of the second path for generating robust test
pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Testpattern verificationof the second path . . . . . . . . . . . . . . . . . . . . . . 41

                                

[1] Feng Lu, Li-C. Wang, Kwang-Ting Cheng, and Ric Huang, “A circuit sat solver with signal
correlation guided learning”, in In Proc. European Design and Test Conference, March 2003.
[2] Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, and Ziyad Hanna, “A signal
correlation guided atpg solver and its applications for solving difficult industrial cases”, in In
Proc. Design Automation Conference, June 2003.
[3] Chih-Ang Chen and Sandeep K. Gupta, “A satisfiability-based test generator for path delay
faults in combinational circuits”, in Design Automation Conference, 1996.
[4] G. L. Smith, “Model for delay faults based upon paths”, in Proceedings of IEEE International
Test Conference, November 1985, pp. 342–349.
[5] C. J. Lin and S.M. Reddy, “On delay fault testing in logic circuits”, in IEEE Trans. Computer-
Aided Design of Integrated Circuits and Systems, September 1987, pp. 694–703.
[6] S. Patil and S. M. Reddy, “A test generation system for path delay faults”, in Proceedings of
IEEE International Conference on Computer Design, October 1989, pp. 40–43.
[7] P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits”,
in IEEE Transactions on Computers, March 1981.
[8] K. Fuchs, F. Fink, and M. H. Schulz, “An efficient automatic test pattern generation system
for path delay faults”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, October 1994.
[9] S. M. Reddy, C. J. Lin, and S. Patil, “An automatic test pattern generator for the detection
of path delay faults”, in Proceedings of IEEE/ACM International Conference on Computer-
Aided Design, November 1987, pp. 284–287.
[10] K.-T. Cheng, A. Krstic, and H.-C. Chen, “Generation of high quality tests for robustly
untestable path delay faults”, in IEEE Transactions on Computers, December 1996.
[11] J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed algorithms to compute tests
to detect and distinguish between failures in logic circuits”, in IEEE Trans. On Electronic
Computers, Oct. 1967.
[12] P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits”,
in IEEE Trans. On Comput., Mar. 1981.
[13] Hideo Fujiwara and Takeshi Shimono, “On acceleration of test generation algorithms”, in
IEEE Transaction On Computer Aided Design, December 1983.
[14] H. K. Tony Ma, S. Devadas, and A. Sangiovanni-Vincentelli, “Logic verification algorithms
and their parallel implementation”, in Design Automation Conf., 1987.

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