對於H.264/AVC迫切所需的硬體加速架構而言，管線化架構已成為普遍採納的解決方法之一，但在管線化架構中，不平衡的時間消耗導致管線化架構的處理能力及硬體使用率降低。在此論文中，我們提出了搭配大區塊層次平行運算的管線化架構設計，為了實現大區塊層次平行架構，我們使用了較傳統大區塊層次管線化更高層次的管線化設計，並且在管線化的每個階段中提出適當的工作管理機制。透過有效的排程演算法及資料同步化處理，可避免在Intra-Prediction及In-Loop Deblocking Filter中的資料相依性問題。並且為了達到擴充性，較以往不同的低階元件也被設計，並符合我們的平行運算架構。為了評估我們所提架構，我們使用FPGA作為實驗的目標平台，從實驗的結果顯示，當使用我們所提之平行架構設計，並且合成在頻率13 MHz時，解碼的速度可達每秒670張QCIF格式的Intra-Frame，或者307張QCIF格式的Inter-Frame。

In urgent demand of hardware architecture design for H.264 coder, pipeline scheme becomes one of most popular solutions. However, the unbalanced time consumption in pipeline stage reduced the throughput and hardware utilization. In this paper, we propose a pipelined architecture with macroblock-level parallelism within pipeline stages. To realize macroblock-level parallelism, higher level pipelining and proper job management between pipeline stages are designed. By efficient scheduling policy and system synchronization, data dependency of intra prediction and in-loop deblocking filter are prevented. In order to highly provide extensibility, possible modifications of low-level modules are employed to match up parallel architecture. To evaluate our proposed architecture, the design is prototyped by using FPGA module as target. From simulation result, while parallel architecture is employed and synthesized in 13MHz, up to 670 QCIF intra frames and 307 QCIF inter frames are decoded per second.

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