本論文主要是設計一個可用於專業影音訊號處理的高速管線化(Pipeline)類比數位轉換器。本類比數位轉換器的目標訂在輸入範圍1 Vp-p，解析度為十位元，最小單位電壓為1 mV，取樣速率為100 MHz。為了實現高速，低功率消耗的轉換效能，採用了管線化架構。在管線化的類比數位轉換器中，由於取樣保值電路為整個管線化類比數位轉換器第一級的電路，它的效能會決定整個管線化類比數位轉換器的表現，所以如何實現一個高速、高準度的取樣保值電路為最主要的設計瓶頸。為了實現這樣一個取樣保值電路，必須設計一個高速、高增益的差動運算放大器。
為了實現一個高速、高增益的差動運算放大器，本設計中使用了訊號加強控制(Gain Boost)與兩級放大(Two stage)的技巧。一般增加增益的方法如串疊電路(Cascode)，因為要增加輸出阻抗才能增加增益，所以會導致單一增益頻寬下降，但是訊號加強控制電路(Gain Boost)使用一個頻寬大於運算放大器本身頻寬的放大器來增加增益，這樣一來，運算放大器本身的單一增益頻寬便不會下降。一般高速、高增益的差動運算放大器如三級串疊電差動運算放大器(Triple cascode Opamp)，在低操作電壓3.3 V的環境下，會有窄輸入共模電位(Input common mode range)、窄輸出擺幅(Output swing)的問題，而兩級放大電路可以藉由分開輸入端與輸出端的電路，使輸入和輸出都以3.3 V的操作電壓進行處理，這樣一來輸入和輸出就有足夠的頭頂空間(Head room)，兩級放大差動運算放大器因而兼有寬輸入共模電位和寬輸出擺幅，將這個優點應用在管線化類比數位轉換器中，每一級的差動運算放大器皆可將全階(Full scale)輸入的差動訊號線性放大兩倍，這樣可以降低下一級處理訊號所需的精確度，這樣一來，越後級的解碼電路便可以使用較低功率消耗的電路來實現，整個電路的功率消耗可以由此降低。
本論文的管線化類比數位轉換器是使用台積電0.25 μm 1P5M mixed-mode的製程來進行模擬設計，使用元件為製程穩定性較高的I/O元件，操作電壓為3.3 V。直流分析模擬是使用Spice來進行模擬，模擬後的數據再利用Matlab進行資料的處理，得到如下的結果：沒有missing code，INL最大值為0.35 LSB，最小值為-0.46 LSB，平均值為-0.08 LSB，而DNL最大值為0.2 LSB，最小值為-0.2 LSB，平均值只有-0.8.3e-17 LSB。至於交流分析同樣使用Spice進行模擬，模擬的數據同樣是利用Matlab來進行資料的處理，所得的交流結果如下：SNDR約為60.6 dB@5 MHz，50.2 dB@40 MHz。本設計的功率消耗為722 mW，使用晶片面積預估約為2000´1000 μm2。因為本設計尚未進行功率最小化的處理，若經過最小化處理後，預估消耗功率約可降低25%左右。

The paper presents a pipeline analog to digital converter (ADC) used for video applications. The 10-bit ADC has an input signal range of ±0.5 V with the resolution near 1 mV. Sampling rate is 100 MHz. To reach the high speed, low power conversion, ADC implemented with pipeline architecture.
How to implement a high speed, high gain Opamp is the bottleneck of ADC design. The Opamp used gain boost and two-stage techniques. Gain boost circuit strengthen the DC gain of Opamp without reducing bandwidth. Two-stage can get wide input common mode range and wide output swing. Pipeline ADC can use this advantage to amplify the full-scale signal stage-by-stage and lower down the precision need stage-by-stage. This will help to save power consumption of pipeline ADC. With the aid of spice and matlab, the simulation DC performance of ADC claims no missing code, DNL within ±0.2 LSB, INL within ±0.5 LSB. The simulation AC performance of ADC claims SNDR are 60.6 dB@5 MHz and 50.2 dB@40 MHz.
The total power dissipation of ADC is about 722 mW. The power reduction can be done using error tolerance of pipeline structure. It is predicted to reduce about 25% of power dissipation.

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