隨著製程的進步，測試的成本的考量變得越來越重要。更複雜的設計，更多的腳位以及更高的工作頻率，都使得測試的工作變成更困難。傳統上解決的方法是使用昂貴的測試機台去維持產品的良率，但這會造成測試成本不斷攀高。為此，我們提出了一種全新的測試方法: HOY。
在我們的所建立的新的測試系統裡，不管是軟硬體都跟原本的測試機台大不相同。為了減少使用者轉移到我們新系統的工作負擔，我們提供了一個能自動產生測試程式的便利工具。使用者可以不用閱讀關於HOY 系統的全部文件，他們僅需要了解如何依造軟體的使用者介面一步一步的操作。而不管是在工程測試的環境或是產品測試的環境，我們的工具都提供相對應的選單去操作。此外，我們的軟體一開始會提供兩種目前已經可以在HOY 測試機台上使用的測試種類，包含記憶體自我診斷測試和邏輯電路自我診斷測試，未來如果機台上測試種類增加，我們也可以在我們軟體上增加它的功能。為了有效的利用我們的測試機台的資源，我們產生出的測試程式將擁有平行測試的功能。如此，整體的測試時間將可以縮小。
在最後我們做了一個簡單的實驗去評估我們的軟體能帶來的好處。不管是產生測試程式的時間或是撰寫測試程式前的預先工作，都可比完全用人工撰寫測試程式來的快速。

With the advance of the IC manufacturing technology, test cost is becoming more and moreimportant. These trends including more complex design, more pin count, and higher working frequency, make IC test more and more difficult. Traditional test technologies use expensive testers to hold product yield and fault coverage, but it makes the test cost ratio of the IC cost increasing. To solve the issue of the test cost, we propose a new test method: HOY (Hypothesis, Odyssey, and Yield).
The hardware and the software of the HOY system are different with traditional test. To reduce the labor effort, we implement a tool to generate the test program for the HOY tester automatically. Hence, users needn't study the documents about HOY, and they just need to operate our tool which includes a graphic user interface step by step. For production test and engineering test, we provide convenient methods to generate test program. Additionally, our tool supports two types of design-for-tests including memory BIST (Built-In Self Test) and logic BIST, and it also keeps the flexibility to expend other test requirements. The test program generated via our tool can also do parallel test, so test time can be reduced.
Finally, we do an experiment to display the advantage of our tool.

[1] Semiconductor Industry Association, "International technology roadmap for semiconductors (ITRS), 2005 edition", Dec. 2005.
[2] C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing, "The HOY tester--Can IC testing go wireless?", in Proc. Int'l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006 (to appear).
[3] P.-K. Chen, Y.-T. Hsing, and C.-W. Wu, "On feasibility of HOY--a wireless test methodology for VLSI chips and wafers", in Proc. Int'l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006 (to appear).
[4] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, "BRAINS: A BIST complier for embedded memories", in Proc. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299--307.
[5] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C-T Huang, and C.-W. Wu, "Automatic generation of memory built-in self-test cores for system-on-chip", in Proc. 10th
IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 91--96.
[6] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester, England, 1991.
[7] C.-F. Wu, C.-T. Huang, and C.-W. Wu, "RAMSES: a fast memory fault simulator", in Proc. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165--173.
[8] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, "A programmable BIST core for embedded DRAM", IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59--70, Jan.-Mar. 1999.
[9] C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "A test access control and test integration system for system-on-chip", in Sixth IEEE Int'l Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1--P2.8.
[10] K.-L. Cheng, J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T. Huang, C.-W. Wu, S.-W. Hung, and J.-Y. Lee, "An SOC test integration platform and its industrial realization", in Proc. Int'l Test Conf. (ITC), Charlotte, Oct. 2004, pp. 1213--1222.