簡易檢索 / 詳目顯示

研究生: 許凱翔
Hsu, Kai Hsiang
論文名稱: 無接觸式堆疊前中介層測試
Contactless Testing for Pre-bond Interposers
指導教授: 張世杰
Chang, Shih-Chieh
口試委員: 麥偉基
陳勇志
錢睿宏
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 37
中文關鍵詞: 中介層測試熱分析機器學習堆疊式晶片
外文關鍵詞: interposer, testing, thermal analysis, machine learning, 3D-IC
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 中介層(interposer)在先進製程封裝佔有舉足輕重的地位,透過將多個晶片堆疊至中介層上,利用中介層做為溝通橋梁可以達到更好的異質整合、更好的效能表現,同時達到更精小的體積尺寸(form factor)。然而,製作上的磨薄程序以及被動元件的性質使得傳統測試機制並不適合用於中介層上,進而增加了可能將損壞中介層堆疊後的額外成本損失。因此,我們提出了一個利用熱影像來區別堆疊前(pre-bond)中介層的好壞的無接觸式測試機制,藉由熱影像,我們從中擷取出缺陷(defect)資訊當作特徵點(feature),並利用機器學習(machine learning)技術自動化判定一個中介層的損壞與否。實驗結果顯示出我們的無接觸式測試機制可以將良率從平均72.13%提昇至96.25%。


    Interposers are essential for integrating multiple dies in staked-die products. However, the traditional testing mechanism is not appropriate for interposers. Therefore, in this work, we proposed a contactless testing methodology for pre-bond interposers. Also, to improve the production yield, surface defects and inner defects will be both examined. Our testing mechanism dedicates to detecting defective interposers by thermal images. Critical features will be extracted from thermal images and will be used to construct machine learning algorithms to determine whether the interposer is defective automatically. Experimental results show that our contactless testing mechanism can efficiently improve the production yield of the interposers from average 72.13% to average 96.25%.

    List of Contents V List of Figures VI List of Tables VII CHAPTER 1 INTRODUCTION 1 CHAPTER 2 PROPOSED TESTING FRAMEWORK 8 CHAPTER 3 SURFACE DEFECT DETECTION 11 3.1 Differential Second Derivative of Two Thermal Images 11 3.2 Feature Extraction of Surface Defects 15 3.3 Classification by K-Means Algorithm 199 CHAPTER 4 INNER DEFECT DETECTION 20 4.1 Difficlut to Solve 20 4.2 Time-Series Second Derivative 151 4.3 Feature Extraction of Inner Defects 26 4.4 SVM for Classification 26 CHAPTER 5 EXPERIMENTS 29 CHAPTER 6 CONCLUSIONS 34 REFERENCES 35

    [1] B.E. Boser, I.M. Guyon, V.N. Vapnik, (1992). A training algorithm for optimal margin classifiers. In Proceedings of the Fifth Annual Workshop of Computational Learning Theory, 5, 144-152, Pittsburgh, ACM.
    [2] W. R. Bottoms, "Test Challenges for 3D Integration (an invited paper for CICC 2011)," Proc. Custom Integrated Circuits Conference (CICC), 2011.
    [3] Y.-W. Chang, C.-J. Hsieh, K.-W. Chang, M. Ringgaard and C.-J. Lin (2010). Training and Testing Low-degree Polynomial Data Mappings via Linear SVM. Journal of Machine Learning Research, 11, 1471 – 1490.
    [4] H. Chen, J. T. Chen, S. J. Lee, K. Chou, C. B. Chen, S. K. Hsu, H. C. Lin, C. N. Peng, and M. J. Wang, “Bandwidth Enhancement in 3DIC CoWoSTM Test Using Direct Probe Technology,” Proc. Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012.
    [5] M. A. Christo, J. A. Maldonado, R. D. Weekly, and T. Zhou, (2011). U.S. Patent No. 7,863,106. Washington, DC: U.S. Patent and Trademark Office.
    [6] C. Cortes, V. Vapnik, (1995). "Support-vector networks". Machine Learning, 20, 273-297.
    [7] S. K. Goel, S. Adham, M. J. Wang, J. J. Chen, T. C. Huang, A. Mehta, F. Lee, V. Chickermane, T. Valind, S. Mukherjee, N. Sood, J. Cho, H. H. Lee, J. Choi, and S. Kim, “Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study,” in IEEE International Test Conference (ITC), pp. 1-10. 2013.
    [8] C.-W. Hsu, C.-C. Chang, C.-J. Lin, (2003). A Practical Guide to Support Vector Classification, Tech. Rep., Taipei.
    [9] K. S. M. Li, S. J. Wang, J. L. Wu, C. Y. Ho, Y. Ho, R. T. Gu, and B. C. Cheng, (2014, November). Optimized Pre-bond Test Methodology for Silicon Interposer Testing. In Test Symposium (ATS), 2014 IEEE 23rd Asian (pp. 13-18). IEEE.
    [10] S. Liu, Y. C. Peng, and F. L. Hsueh, “Special considerations for 3DIC circuit design and modeling,” in IEEE International Conference on IC Design&Technology, 2011.
    [11] E. J. Marinissen, “Testing TSV-Based Three-Dimensional Stacked ICs,” Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010.
    [12] E. J. Marinissen, and Y. Zorian, “Testing 3D Chips Containing Through-Silicon Vias,” Proc. International Test Conference (ITC), 2009.
    [13] J. Park, Y. B. Jo, J. K. Park, and G. R. Kim, (2008). Propensity of copper dendrite growth on subassembly package components used in quad flat package. Device and Materials Reliability, IEEE Transactions on, 8(2), 368-374.
    [14] M. Taouil, S. Hamdioui, and E. J. Marinissen, “How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs,” Proc. Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011.
    [15] W. T. Tseng, D. Canaperi, A. Ticknor, V. Devarapalli, L. Tai, L. Economikos, J. MacDougal, M. Angyal, J. Muncy, X. Chen, J. Zhang, Q. Fang, J. Zheng, (2012, May). Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes. In Advanced Semiconductor Manufacturing Conference (ASMC), 2012 23rd Annual SEMI (pp. 57-62). IEEE.
    [16] T. Tun, S. Zhigang, K. Yoges, C. K. Oh, and K. F. Lo, (2004, December). Copper dendrite growth and analysis on copper damascene process. In Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on (pp. 3-pp). IEEE.
    [17] R. Wang, Z. Li, S. Kannan, and K. Chakrabarty, (2016, March). Pre-bond testing of the silicon interposer in 2.5 D ICs. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 97 8-983). IEEE.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE