隨著半導體製程的快速發展，半導體記憶體的大小及密度迅速成長，而維持高水準的品質（Quality）、良率（Yield）與可靠度（Reliability）也越來越困難。冗餘修復（Redundancy Repair）技巧與錯誤更正碼（Error Correction Code, ECC）是常用來增進記憶體晶片良率與可靠度的兩種方法。傳統上，前者是用來修復硬錯誤（Hard Error），後者則是用來更正軟錯誤（Soft Error）。在本篇文章中，我們提出一個整合型的解決方案以增進記憶體之可靠度。過去相關的研究結合冗餘修復技巧與錯誤更正碼都是為了提高記憶體之良率，出廠前所測到的部份缺陷並沒有完全利用冗餘單元作永久修復，而是利用錯誤更正碼的更錯能力讓使用者在使用時能更正錯誤的資料。現代互補型金屬氧化物半導體（CMOS）記憶體容易受到放射線所引起的軟錯誤，因此，以可靠度的觀點，錯誤更正碼更正軟錯誤的
能力不應該被犧牲。我們所提出的方法則是在使正常操作模式（Normal Operation Mode）時能配合錯誤型態辨別方法分辨硬錯誤與軟錯誤，並在記憶體空載時間（Memory Idle Time）將硬錯誤用還沒有被使用的冗餘單元修補，使有錯誤更正碼電路的記憶體可以容忍更多的軟錯誤且不會損壞。我們並提出了ㄧ個估計記憶體可靠度的方法。實驗結果顯示藉由提出的整合冗餘修復與錯誤更正碼的方法，記憶體大小為8kx64 的平均故障間隔時間（Mean Time to Failure, MTTF）可提高1412 小時（7.1%）。
另一方面，由於進入深次微米技術，為了維持記憶體產品的可靠度以及品質，錯誤更正碼要同時能容忍更多數目的錯誤。然而，雙錯誤更正能力的錯誤更正碼（Double-Error Correctable ECC）卻很少被設計在記憶體電路中，因為其所需較多的校驗位數目（parity-bit）以及複雜的編碼解碼步驟使得成本過高。本篇文章提出一個低成本具有雙錯誤更正能力的方法，其所需要的校驗位數目與傳統具單錯誤更正-雙錯誤偵測能力的錯誤更正碼（Single-Error Correctable and Double-Error Detectable ECC）相同。

With the fast development pace of deep submicron technology comes a rapid growth in the size and density of semiconductor memory. However, keeping a high level of yield and reliability for
memory products becomes increasingly difficult. Both the redundancy repair and Error Correction
Code (ECC) techniques have been widely used for enhancing the yield and reliability of memory
chips. Specifically, the redundancy repair and ECC techniques are conventionally used to repair or
correct the hard faults and soft errors, respectively. In this paper, we propose an integrated ECC and
redundancy repair scheme for memory reliability enhancement. Previous works emphasized yield
improvement as they combined redundancy repair and ECC schemes, while we develop a method
to permanantly repair hard errors in the field so that more soft errors can be tolerated without chip
failure. Our approach identifies the hard faults and soft errors during the memory normal operation
mode, and repairs hard faults during the memory idle time as long as there are unused redundant
elements. A method for evaluating the memory reliability is also developed. Experimental results
show that the proposed approach is effective, e.g., the MTTF of an 8K 64 memory is improved
by 1,412 hours (7.1%) with our integrated ECC and repair scheme.
In addition, the development of deep submicron technology causes the semiconductor memory
to become larger and denser. In order to maintain high reliability and quality for memory products,
ECC buth serves as a soft error correction and plays an important role in reliability enhancement
to tolerate other forms of hard errors. However, double-error correctable (DEC) ECC has rarely
been used in memory designs because of its high cost in parity area overhead and the complex
calculation process. In this paper, we also propose a low-cost double-error correctable scheme
without expanding the number of parity bits required in traditional single-error correctable and
double-error detectable (SEC-DED) ECC. Experimental results show that the proposed method
has a low area overhead with no increase in the decoding cycles compared to conventional double
error correctable and triple-error detectable (DEC-TED) ECC (BCH code).

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