鎖相迴路在時脈的產生與同步方面有著非常多的應用, 其時脈的品質對系統的效能有決定性的因素. 在這個SoC時代, 越來越多模組整合進同一顆晶片, 從電源來的雜訊就越來越大且其效果也越來越顯著. 目前已有很多作品去探討電源雜訊如何使系統的效能變低落, 也提出了一些改善的方法[4], [7], [8],[10]。

在這篇著作裡, 我們利用寬可調範圍200MHz到1.6GHz的環震盪器來設計並實現鎖相迴路. 此外, 我們因為current-starved架構有著滿幅震盪的特性, 所以我們挑選此做為延遲單位, 雖然環震盪器比LC震盪器較受電源所影響. 在這設計中, 我們在不同的操作頻率下選擇適當的電流鏡比例以達到訊號擺幅和充電電流的最適當平衡. 而藉此可在所有可調範圍下達成低電源敏感度的特性.

我們量測到的震盪器在其可調範圍內電源敏感度由-0.9%/%到1%/%. 而其在500MHz到1.2GHz中有很接近零的電源敏感度. 在給10mV, 20MHz的電源雜訊時, 此鎖相迴路的峰對峰絕對擾動小於20%的震盪週期, 而其峰對峰的週期擾動小於4%的震盪週期. 整體鎖相迴路在最高頻1.6GHz時需要36.17mW的功率消耗.

Phase-locked loops are widely used in many applications for clock
generation and synchronizations. The signal’s timing quality is
of critical importance to the system’s performance. As more and
more modules are integrated into the same chip in SoC era, the noise on the supply rails becomes larger and more significant.
Many prior works have investigated the performance degradation due to supply noise and proposed techniques for improvement[4], [7], [8], [10].
In this work, we have designed and implemented a PLL using a CMOS ring oscillator for its wide tuning range from 200 MHz to 1.6 GHz. Furthermore, current-starved structure is used for delay cells for its rail-to-rail characteristics. However, ring oscillators are more susceptible to supply noise than the LC counterpart. In
this design, the current mirror ratio is changed according to the operating frequency for optimal balance between the signal swing and charging current. This leads to low supply sensitivity over the tuning range.
The measured supply sensitivity is from 􀀀0.9%/% to 1%/% over the entire tuning range, and is close to zero for 500 MHz to 1.2 GHz. The peak-to-peak absolute jitter is measured to be less than 20% of the oscillation cycle with 10-mV supply noise at 20MHz, and the peak-to-peak cycle jitter is measured to be less than 4%. The entire PLL consumes 36.17 mW at 1.6 GHz.

[1] F. Herzel, B. Razavi, ”A Study of Oscillator Jitter Due to Supply and Substrate
Noise.” IEEE Circuits and Systems Society, vol. 46, no.1, pp. 56–62, Jan. 1999.

[2] X. Ge, M. Arcak, K.N. Salama, ”Nonlinear analysis of ring oscillator circuits.”
American Control Conference (ACC), pp. 1772–1776, Jan. 2010.

[3] B. Razavi, ”A study of phase noise in CMOS oscillators.” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331–343, Mar. 1996.

[4] P. Hsieh, J. Maxey, C.-K. K. Yang, ”Minimizing the Supply Sensitivity of
a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages.” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2488–2495, Sept. 2009.

[5] E. Soleiman, Kamarei, Mahmoud, ”New low current mismatch and wide output dynamic range charge pump.” Electrical Engineering (ICEE), pp. 1–5, May 2011.

[6] J.G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques." IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Sept. 1996.

[7] T. Wu, K. Mayaram, U. Moon, ”An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Sept. 2007.

[8] C. Lai, M. Shen, Y. Wu, K. Huang, P. Huang, ”A 0.24 to 2.4 GHz phaselocked loop with low supply sensitivity in 0.18-μm CMOS.” Circuits and Systems (ISCAS), pp. 981–984, 2011.

[9] S. Kao, S. Liu, ”A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. ” Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 592–602, 2011.

[10] M. Mansuri, C.-K. K. Yang,”A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation.” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, 2003.

[11] J. Lee, B. Kim, ”A low-noise fast-lock phase-locked loop with adaptive bandwidth control.” IEEE J. Solid-State Circuits , vol. 35, no. 8, pp. 1137–1145, Aug. 2000.

[12] E. Alon, J. Kim, S. Pamarti, K. Chang, M. Horowitz, ”Replica compensated linear regulators for supply-regulated phase-locked loops.” IEEE J. Solid-State Circuits , vol. 41, no. 2, pp. 413–424, Feb. 2006.