RISC-V 指令集在近年來越來越受歡迎。作為一種指令集架構(ISA)， 它不僅允許開發者設計自訂指令，還可能支持 VLIW 編碼。VLIW 代表 超長指令字(Very Long Instruction Word)，它表示一種能夠同時執行一 組指令的架構，從而利用指令級並行性來提高性能。主要由張量操作組 成的應用程序，如多媒體和計算機視覺，通常透過部署在採用 VLIW 架 構的數字信號處理器(DSP)上進行優化。本論文重點探討了為 RISC-V VLIW 架構構建 LLVM 編譯器，以探索此類配置的潛力。我們提出了一 種六發射 RISC-V VLIW 架構，該架構包括兩個整數單元、兩個浮點或雙 精度單元以及兩個向量單元。本文集中於在 LLVM 後端中建立 RISC-V VLIW 目標，展示了實作 LLVM 後端目標以及生成 VLIW 組合語言的必 要步驟。除了實作 LLVM 後端外，我們還為我們的目標整合了 Modulo Scheduling 演算法。在生成 RISC-V 向量指令集組合語言的過程中，我們 會利用 LMUL 功能將多個向量暫存器組合在一起，從而增加向量長度。然 而，必須考慮向量長度增加與指令排程期間可能出現的暫存器溢出的狀 況。這個狀況起因於隨著更多向量寄存器被組合在一起，可用的暫存器資 源減少，增加了指令排程階段暫存器溢出的可能性。為了解決這一問題， 我們開發了一個方程式來估計出對於該段迴圈比較適合的 LMUL 值。我們 進行的實驗包括在啟用了 Swing Modulo Scheduling 和未啟用的情況下對 我們提出的 VLIW RVV 架構進行性能比較。根據我們使用 DSP Stone 基準測試的實驗，我們觀察到了 0.2% 至 35% 的性能提升。

The RISC-V instruction set has gained increasing popularity in recent years. As an instruction set architecture (ISA), it not only enables developers to design custom instructions but also potentially supports VLIW encoding. VLIW, standing for Very Long Instruction Word, represents an architecture that concurrently executes a group of instructions, thereby leveraging the benefits of instruction-level parallelism to enhance performance. Applications largely composed of tensor operations, such as multimedia and computer vi- sion, are frequently optimized by deploying these applications on Digital Sig- nal Processors (DSPs) that adopt VLIW architectures. This paper focuses on the construction of LLVM compilers for RISC-V VLIW architectures to explore the potential of such configurations. We propose a 6-way RISC-V VLIW architecture, comprised of two integer units, two floating point or double precision units, and two vector units. The paper concentrates on the establishment of a RISC-V VLIW target within the LLVM backend, demon- strating the process of implementing an LLVM backend target and the neces- sary steps for generating VLIW assembly code. Beyond the implementation of the LLVM backend, we also integrate Modulo Scheduling for our target. In the process of generating RISC-V Vector Extension code, we leverage the LMUL feature to group multiple vector registers together, thereby enhancing vector length. However, it’s essential to consider the trade-off between increased vector length and potential register spilling during scheduling. As more vector registers are grouped together, the available register resources decrease, it increases the likelihood of register spilling during the scheduling phase. To address this, we have developed a heuristic equation to deter- mine the feasible LMUL. The experiment conducted involves a performance comparison between scenarios with and without Swing Modulo Scheduling enabled for our proposed VLIW RVV architectures. Based on our experimen- tation with the DSP Stone benchmark, we observed a performance increase ranging from 0.2% to 35%.

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