在先進技術節點中，每個標准元件可能在元件庫當中有多個實體設計。這些實體設計被稱為元件版本，它們可能有不同的面積、功耗和驅動強度。這使得元件庫能夠更靈活得滿足不同的設計限制。本文中所採用的混和列高設計擁有兩種不同的列高，也就是矮和高。相對應的元件庫中每個元件有著不同高度的元件版本像是矮、高和雙列高。和具有混和元件高的單列高設計相比，混和列高設計所需較小的晶片面積。混和列高設計的其中一個限制是每個元件只能被擺置在有合適列高的列上。文中採用的設計中，只有一部分元件可以變更版本，我們稱那些元件為彈性元件。我們可以對彈性元件進行版本替換來達成合理的資源使用。其餘被限制版本的元件我們稱之為非彈性元件。儘管混和列高設計有多項優點，擺置問題變得更加複雜。

在本文中，我們提出一個考量混合列高設計列配置的全局佈局。我們的方法不只消除擺置區域上的壅擠點，也適當的擺置那些非彈性元件。由於在本文中考量到了列配置所以在合法化階段時可以花費較少努力。我們方法的主要貢獻是在細部階段中有效的消除壅塞點。與先前的研究相比，實驗結果顯示我們在合法擺置的半周長線長可以減少約3%及在合法化階段的元件位移減少約30%。

In advanced technology nodes, each standard cell may have multiple physical implementations in the cell library. Those implementations are called cell versions; they may have different areas, power consumption, and driving strength. It makes the cell library more flexible to meet different design constraints. The mixed-row-height design adopted in this paper has two different row heights, i.e., short and tall. The corresponding cell library also contains versions with different heights such as short, tall, and double-row height for each standard cell. Compared to the uniform-row-height designs with mixed cell height, the hybrid-row-height design can result in a smaller required chip area. One of the constraints of mixed-row-height designs is that each cell can only be placed on rows with proper row height. In the adopted designs, only part of cells can change their versions, and we call those cells flexible cells. We can perform version substitution on flexible cells to maintain reasonable resource usage. The other cells which cannot change the cell versions are called non-flexible cells. Although the mixed-row-height designs have many advantages, the placement problem becomes more complicated.

In this paper, we propose a row configuration aware global placement for advanced mixed-row-height designs. Our approach not only eliminates congestion in the placement region but also properly places those non-flexible cells. As a result, the legalization stage can take less effort from the row configuration awareness in this paper. The main contribution of our approach is the efficient congestion elimination in the refinement stage. Compared with the previous work, the experimental results show that our approach can reduce about 3% on the half-perimeter wirelength of the legalized placement and about 30% on the displacement of cells in the legalization stage.

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