隨著深度學習神經網路的快速發展以及行動裝置的廣泛應用，資料的計算及傳輸數量急遽成長。然而，傳統處理器范紐曼(Von Neumann)架構，受限於資料傳輸的速度、硬體成本，以及能量的消耗，因此記憶體內運算便成為一個具潛力之解決方案，能夠將傳統架構所需的資料交換過程於記憶體內部完成。
深度學習神經網路通常需要m層卷積層(Convolution Neural Network)以及n層全連接層(Fully-Connected Network)，然而，除了大量的資料集存取時間外，卷積神經網路以及全連接網路的乘加運算，亦會產生大量的中間資料(intermediate data)，因此，實現具高密度之非揮發性記憶體內的運算，能夠避免范紐曼架構受限之資料傳輸速度、減少中間資料的搬移，並且縮短一個記憶體運算週期內所需的乘加運算時間，大幅提升深度學習神經網路的運算速度。
本篇論文透過0.18µm邏輯製程，以模擬結果實現了容量為1Mb，基於電阻式記憶體(ReRAM)之卷積神經網路的加速運算，具二進制輸入及三元權重(Binary Input Ternary Weight)之乘積和(Product Sum)，使用3 x 3 kernel完成一次乘加運算於2bits輸出模式之讀取時間為37.5ns，3bits輸出模式為50ns.

With the rapid development of the deep neural network and the widely popular of variety mobile devices, the number of computing data and transmission has rapid grown. However, the conventional Von Neumann architecture are limited by the transmission speed, hardware costs and energy consumption. Therefore, the computing in memory has become a solution with high potential, that the conventional data exchange could be process in memory directly.
The deep neural networks usually require m-layers of the convolution neural networks (CNN) and n-layers fully-connected networks (FCN). However, except the heave access time generated from amounts of data sets, it also generated large amounts of the intermediate data due to the multiply-and-accumulate (MAC) operations for CNN and FCN. Therefore, demonstrate a compute-in memory(CIM) approach with high-density NVM could avoid the limit of conventional Von Neumann architecture transmission speed, reducing the intermediate data access, and reduce the latency of the MAC operations in one cycle, can enhance the DNN operations speed greatly.
Based on 0.18um CMOS logic process, we fabricated a 1Mb computing-in-memory ReRAM macro with Multiply-and-Accumulate operation and BITW structure for DNN by simulation. This work achieves 37.5ns access time for CNN operation using 3x3 kernels in 2bits sensing mode, and 50ns access time in 3bits sensing mode.

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