研究生: |
盧承宏 Cheng Hong Lu |
---|---|
論文名稱: |
300V溝渠式與P型場環體橫向雙擴散金氧半場效電晶體之設計 The Design of 300V Trench and P-ring LDMOSFET |
指導教授: |
龔正
Jeng Gong |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 產業研發碩士積體電路設計專班 Industrial Technology R&D Master Program on IC Design |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 溝渠 、P型場環體 、橫向雙擴散金氧半場效電晶體 |
外文關鍵詞: | trench, P-ring, LDMOS |
相關次數: | 點閱:1 下載:0 |
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功率元件為了與平面製程整合,必須將傳統垂直式的元件結構改成橫向式的設計,因而可與低壓電路整合於同一晶片上。本論文探討的主軸結構為Trench LDMOSFET,其特性為在結構中閘極下方的漂移區內填入二氧化矽,使得導通電阻與元件面積獲得到比傳統LDMOSFET更佳的元件性能。
本篇論文將Trench SiO2與P-ring結合於傳統LDMOSFET中作整合分析。改良傳統Trench LDMOSFET過長的溝渠使用,加入的P型場環體(P-internal field ring)讓元件整體的RESURF效果發揮更卓越;在固定元件尺寸之下的改良式結構比起傳統式結構可以擁有更優越的效能,而我們定義這種改良式結構為複合式LDMOSFET。
最後將透過電腦模擬的方式,可以清楚知道在不同條件設定下的崩潰電壓與導通電阻,有效的掌握其結構於最佳化的過程中,經過不斷地相互制衡後最終達到此次設計的目標300V,使得在同一尺寸下的元件能充分發揮空間利用率,並提出此複合式結構於未來開發的可能性。
In order to integrate power devices with planar IC process, the devices structure must be changed from the traditional vertical structure to lateral design, such that they can be integrated in the same chip. The main object of this thesis is Trench LDMOSFET. The characteristic of the structure is to fill a SiO2 trench in the drift region under the gate, to decrease on-resistance and to produced better effect than traditional LDMOSFET.
In this thesis, we integrate the oxide trench and P-ring into traditional LDMOSFET to further improve the performance of RESURF LDMOSFET. Devices’ performance is compared in the base of the same size.
Finally, we use computer simulation to obtain the detail of breakdown voltage and on-resistance under different situations. Careful tuning is made to obtain the optimum process conditions. The goal reached is that the device can resist 300V breakdown voltage. The efficiency of the traditional device is indeed reinforced, and the results of the simulation also create the possibility of developing the complex structure in future.
[1] Michael S. Adler, King W. Owyang, amd B. Jayant Baliga,
“The Evolution of Power Devices Technology”, IEEE Trans.
Electron Devices, vol. ED-31, pp.1570-1591, Nov. 1984.
[2] S. Hidalgo, J. Fernandez, P.Godignon, J. Rebollo, and J. Millan
“POWER LATERAL DMOS TRANSISTOR TEST STRUCTURES ”, ICMTS vol. 6, pp. 33-38, Mar. 1993.
[3] Robert F. Pierret, Semiconductor Devices Fundamentals,
Copyright 1996 by Addison-Wesley Publishing Company, Inc.
[4] S. Colak, B. Singer, E. Stupp, “Lateral DMOS Power Transistor Design”, IEEE Electron Device Letters, vol. EDL-1, pp. 51-53, 1980.
[5] R. Jayaraman, V. Rumennik, B. Singer, E.H. Stupp, “Comparison of high voltage devices for power integrated circuits ”, IEDM, vol. 30,
pp. 258-261, 1984.
[6] B. J. Baliga, Power Semiconductor Devices, Copyright 1996 by PWS
[7] Adriaan W. Ludikhuize “Performance and Innovative Trends in RESURF ”, ESSDERC 2001 , pp. 35-44, Sep. 2001.
[8] J. A. Appeals, and H. M. J. Vaes, “High-voltage thin layer devices (RESURF devices)”, IEDM Tech. Dig., pp. 238-239, 1979.
[9] Zahir Parpia, and C. Andre T. Salama, “Optimization of RESURF LDMOS transistors: an analytical approach”, IEEE Electron Device, vol. ED-37, No. 3, pp. 789-795, 1990.
[10] F. Conti and M. Conti,“Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate”,Solid-State Electronics, vol. 15, pp.93-105, 1972.
[11] Merchant, S.; Arnold, E.; Baumgart, H.; Egloff, R.; Letavic, T.; Mukherjee, S.; Pein, H. , “Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors”, ISPSD '93, pp.124-128
[12] Zitouni, M.; Morancho, F.; Rossel, P.; Tranduc, H.; Buxo, J.; Pages, I. ,“A new concept for the lateral DMOS transistor for smart power IC's”, ISPSD '99, pp.73-76
[13] W. Ludikhuize, “Design aspect of high voltage devices for a 700-1200V IC process”, Proc. Symp. on High Voltage and Smart Power ICs, pp. 133-138, 1989.
[14] AVANT! TSUPREM-4, Two-Dimensional Process Simulation Program,Version-2000.4.0
[15] AVANT! MEDICI, Two-Dimensional Device Simulation Program, Version-2000.4.0
[16] .-K. Kwon, T. Eand, W. T. Ng, S. Malhi, R. Todd and J. K. Lee,
“Optimized 60-V Lateral DMOS devices for VLSI power applications”,Digest of Technical Paper Symposium on VLSI Technology, pp. 115-116, May 1991.
[17] Won-So Son, Young-Ho Sohn and Sie-Young Choi“Effects of a trench under the gate in high voltage RESURF LDMOSFET for SOI power integrated circuits”,Solid-State Electronics, Vol. 48,Iss 9, pp. 1629-1635, September 2004.
[18] Nezar and C. A. T. Salama, “Breakdown voltage in LDMOS transistors using internal field rings”, IEEE Trans. Electron Devices, Vol. 38, No. 7, July 1991.
[19] C. Basavana Goud, K. N. Bhat, “Breakdown voltage of field plate and field-limiting ring techniques: numerical comparison”, IEEE Trans. Electron Devices, Vol. 39, No. 7, July 1992.
[20] 王國榮, “200V 溝渠式橫向雙擴散金氧半場效電晶體之設計”‚碩士論文‚國立清華大學電子工程研究所‚2005
[21] 蔡佳宏‚“200V P型環橫向雙擴散金氧半場效電晶體之設計” ‚碩士論文‚國立清華大學電子工程研究所‚2006
[22] Min Liu‚C. A. T. Salama, P. Schvan and M. King, “A fully resufed,BiCMOS-compatible, high voltage MOS transistor”,ISPSD
′96, pp.143-146