非晶矽薄膜電晶體(a-Si TFT) 因在大面積基板上有好的均勻度、低製程溫度、以及高生產良率, 而成為主動式矩陣液晶顯示器(AMLCD)的主流技術。 近幾年為了降低成本的考量, 於顯示器的應用上, 在玻璃基板上使用中大尺寸非晶矽薄膜電晶體當閘極驅動電路 (gate driver circuits) 吸引了不少的注意力。 玻璃基板上積體化閘極驅動電路 (GOA) 的生命週期與特性主要被大尺寸非晶矽薄膜電晶體的電特性所影響, 例如長時間操作下的門檻電壓飄移 (△Vth)。 在本篇論文中, 為了改善大尺寸非晶矽薄膜電晶體的電特性, 我們廣泛地探討製程改善方法並評估這些製程對元件電特性的影響。 再者, 為了符合積體化閘極驅動電路元件實際使用在玻璃基板上的狀況, 本篇論文中討論的大尺寸非晶矽薄膜電晶體, 其通道寬度 (channel width) 在 1000 到 10000微米的範圍。
首先, 我們使用並探討了一種最佳化製程整合閘極絕緣層 (GI) 跟本質非晶矽層 (intrinsic a-Si layer) 到大尺寸非晶矽薄膜電晶體的製程上。 我們也設計了不同通道寬度的元件來研究元件尺寸的影響。 根據實驗結果, 我們觀察到大尺寸非晶矽薄膜電晶體的初始電特性, 如電流-電壓特性, 並沒有被最佳化製程整合影響。 我們也量測了不同溫度底下, 元件的漏電流 (Ioff)。 我們發現最佳化製程整合可以讓大尺寸非晶矽薄膜電晶體漏電流顯著下降, 這是因為漏電流的活化能 (Ea) 上升。 此外, 我們將高、低電場的直流電應力施加在元件閘極上, 來研究最佳化製程整合對元件不穩定性的影響。 從實驗數據中發現, 使用了最佳化製程整合後, 大尺寸非晶矽薄膜電晶體的門檻電壓飄移能有效的下降。 再者, 在高和低電場電應力下, 元件門檻電壓飄移的主因都是本質非晶矽層內的缺陷產生。
第二部分, 為了進一步改善大尺寸非晶矽薄膜電晶體的電特性, 我們分別利用氫氣在本質非晶矽層沉積前對閘極絕緣層做前通道處理 (FCT), 以及在本質非晶矽層沉積後對元件背通道做處理 (BCT)。 然而, 根據我們的實驗結果, 發現前通道處理製程會使元件的門檻電壓飄移更惡化, 這是因為影響門檻電壓飄移的主因是本質非晶矽層內的缺陷產生, 而對閘極絕緣層做前通道處理無法減少缺陷的產生。 此外, 由我們的數據顯示, 對閘極絕緣層做前通道處理製程可能對元件通道的表面產生傷害, 使得元件穩定性變差, 而無法改善元件的門檻電壓飄移。 不過, 當我們對元件使用背通道處理並最佳化製程時間, 我們觀察到大尺寸非晶矽薄膜電晶體的漏電流和受過高、低電場應力下的門檻電壓飄移都顯著的減少。 由漏電流的數據顯示, 我們發現較短或是較長時間的背通道處理製程並不利於降低元件的漏電流。 而從門檻電壓飄移的數據看到, 元件在受過高電場應力後, 影響元件門檻電壓飄移的主要機制是非晶矽層內的缺陷產生, 而不是閘極絕緣層內的電荷捕捉所主導, 這跟先前文獻所提的狀況不同。 這個不同可能是因為元件閘極絕緣層內膜質和先前文獻不同, 而和元件尺寸無關。

Amorphous silicon thin-film transistor (a-Si TFT) is the mainstream technique for active-matrix liquid crystal display (AMLCD), due to a good uniformity over large-area substrates, low process temperature, and a high production yield. In recent years, for cost-reduction consideration, using medium- and large-sized a-Si TFTs to form the gate driver circuits integrated on array glass substrate has attracted a lot of attention in display application. The lifetime and performance of integrated gate driver on array substrate (GOA) are dominated by the electrical characteristics of large-sized a-Si TFTs, such as threshold voltage shift (△Vth) under a long-term operation. In this thesis, to improve the electrical characteristics of large-sized a-Si TFTs, we extensively studied the process improvements and evaluated the influences of these processes on the electrical performance of devices. In addition, the channel width of large-sized a-Si TFTs studied in this thesis is ranged from 1000 to 10000 µm for being comparable to practical devices used in GOA.
At first, an optimal process integration on GI and intrinsic a-Si layer of large-sized a-Si TFTs was applied and investigated. Different channel widths were designed to discuss the effect of sample size. Based on the experimental results, it was observed that the initial electrical characteristics of large-sized a-Si TFT were not influenced by optimal process integration, such as current-voltage characteristics. The off current (Ioff) of devices at different temperatures were measured as well. It was found that Ioff of large-sized a-Si TFTs could be remarkably reduced by optimal process integration, since the activation energy (Ea) of Ioff was increased. In addition, the DC stresses with high and low electrical fields were applied on the gate electrode of devices to study the instability influenced by the application of optimal integration. It was experimentally found that △Vth of large-sized a-Si TFTs could be effectively reduced by optimal process integration. In addition, the defect generation in a-Si layer was the dominated mechanism for the △Vth of devices under high and low electrical-field stresses.
In the second part, to achieve further enhancements of electrical characteristics for large-sized a-Si TFTs, a front-channel treatment (FCT) with hydrogen gas on GI layer prior to the deposition of intrinsic a-Si layer and a back-channel treatment (BCT) with hydrogen gas after the deposition of intrinsic a-Si layer were applied and investigated, respectively. However, based on our experimental results, it was found that the △Vth of devices was more by the FCT, since the dominated mechanism of △Vth was defect generation in a-Si layer, which would not be reduced by the FCT on GI layer. In addition, from the observation of our data, the FCT on GI layer might cause damage to the surface of channel for devices, leading to a worse stability, instead of reducing the △Vth of devices. Besides, by applying BCT and optimizing the process time, it was observed that Ioff and △Vth of large-sized a-Si TFTs after high and low electrical-field stresses were remarkably decreased. For the experimental results of Ioff, it was found that a shorter or a longer BCT process time for devices were unsuitable for reducing the Ioff of devices. As for the results of △Vth, the dominated mechanism responsible for △Vth of devices after a high electrical-field stress was defect generation in a-Si layer rather than charge trapping in GI layer, which is different from previous studies. The difference may be caused by the different GI quality of devices, not the sample size.

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