時脈抖動內建自我測試之電荷幫浦鎖相迴路｜國立清華大學博碩士論文庫

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研究生：	林昆易 Lin, Kun-I
論文名稱：	時脈抖動內建自我測試之電荷幫浦鎖相迴路 BIST for Jitter Measurement of Charge-Pump Phase-Locked Loop
指導教授：	張慶元 Chang, Tsin-Yuan
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	86
中文關鍵詞：	鎖相迴路
外文關鍵詞：	Phase-Locked Loop
相關次數：	點閱：2 下載：0
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由於現今數位系統的時脈訊號頻率愈來愈高，意謂著常用來作為數位系統中頻率產生器（Clock Generator）的鎖相迴路，其輸出頻率也得愈作愈快，使得以往量測鎖相迴路時脈抖動的方式已不再適用，所以近來做時脈抖動的量測，較為有效且精確的方式，則是使用內建晶片式時脈抖動量測（On-chip Jitter Measurement）。
本篇論文提出了一時脈抖動內建自我測試（Built-in Self Test）之電荷幫浦鎖相迴路的架構，此架構亦屬於內建晶片式時脈抖動量測，相較於先前的時脈抖動內建自我測試架構，本篇論文所提出的架構改變了計數器（Counter）的位置，使得量測解析度（measurement　resolution）得以提高，再者重新設計了電荷幫浦電路（Charge Pump），使其充電電流在不同的壓控振盪器之控制電壓下更趨於穩定，使得量測誤差（measurement error）得以降低，另外架構中所提出的數位控制單元（Digital Control Unit），目的除了在切換不同的量測模式之外，亦大大降低了量測時間（measurement time），使得壓控振盪器之控制電壓因漏電流（leakage current）現象所造成的改變量減少，亦使得量測誤差得以降低，最後由模擬結果可顯示出此一時脈抖動內建自我測試之電荷幫浦鎖相迴路架構其量測解析度可達約1ps，而量測誤差可降低至15%以下。

This thesis proposes a BIST architecture for measuring the period jitter which is represented in two types of peak-to-peak jitter and rms jitter in Charge-Pump PLLs. Comparing with previous BIST circuit, the proposed BIST circuit changes the counter position to increase the measurement resolution and modifies the Charge Pump circuit of TDC to reduce the measurement error. The proposed digital control unit can decrease the testing time that also improves the leakage current effect. Thus, the measurement error is therefore reduced. The simulation results shows that the measurement resolution is about 1ps and that the measurement error is smaller than 15%.

誌謝……………………………………………………………………    2
中文摘要………………………………………………………………    3
Abstract………………………………………………………………..    4
List of Contents………………………………………………………..    5
List of Figures…………………………………………………………    8
List of Tables………………………………………………………….    12
Chapter 1.  Introduction……………………………………………..    13
       1.1 Motivation……………………………………………….    13
       1.2 Jitter Definition………………………………………….    14
         1.2.1 Cycle-to-Cycle Jitter………………………………..    15
         1.2.2 Period Jitter……………………………..…………..    16
         1.2.3 Long-Term Jitter…………...………………………..    17
       1.3 Organization of Thesis…………...............………………    18
Chapter 2.  PLL Function…………………………………..………..    19
      2.1 PLL Overview……………………………………………    19
         2.1.1 PFD (Phase-Frequency Detector)……………………    21
         2.1.2 CP (Charge Pump) ………………………………….    23
         2.1.3 LF (Loop Filter)……………………………………..    25
         2.1.4 VCO (Voltage-Control Oscillator) …………………    27
         2.1.5 FD (Frequency Divider) ……………………………    30
        2.2 PLL Analysis……………………………………………..    32
         2.2.1 Frequency-Domain Open-Loop Analysis……………    32
         2.2.2 Frequency-Domain Close-Loop Analysis…………..    34
         2.2.3 Time-Domain Close-Loop Analysis…………………    36
Chapter 3.  Previous Jitter Measurement……….……………………    42
       3.1 Conventional Off-Chip Jitter Measurement……..………    42
       3.2 Previous Works of On-Chip Jitter Measurement…...……    43
         3.2.1 Vernier Delay Line………………….………………    43
         3.2.2 Analog-to-Digital Converter………………………..    45
         3.2.3 Time-to-Digital Converter………………………….    46
       3.3 Previous BIST Architecture…………………………….    48
Chapter 4.  Proposed BIST Architecture……………………………    50
       4.1 Proposed Phase-Frequency Detector……………………    50
       4.2 Proposed Charge Pump (CP2) Circuit…………………..    52
       4.3 Proposed Frequency Divider…………………..………..    54
       4.4 Proposed Digital Control Unit…………………………..    56
         4.4.1 Proposed Lock Detector (LD)……………………...    59
         4.4.2 Proposed Phase-Capture Unit (PCU)........................    61
         4.4.3 Proposed BIST Cycle Generator...............................    62
Chapter 5.  Simulation Result ………………………..……………..    63
       5.1 Pre-Layout Simulation…………………………………..    64
       5.2 Layout and Post-Layout Simulation………………….....    72
         5.2.1 Layout ……………………………………………...    72
         5.2.2 Post-Layout Simulation ………………………….....    75
       5.3 Specifications and simulation results………………..…..    79
       5.4 Comparisons……………………………………………..    80
Chapter 6.  Conclusion and Future Work …………………………...     82
       6.1 Conclusion………………………………………………    82
       6.2 Future Work……………………………………………..    83
Bibliography…………………………………………………………..    84

                                

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