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研究生： 李明和
論文名稱： 高速的AES加密解密晶片設計
A Gbps AES Cipher
指導教授： 林永隆
Youn-Long Lin
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2001
畢業學年度： 89
語文別： 中文
論文頁數： 44
中文關鍵詞： AES演算法
外文關鍵詞： AES Algorithm
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    • 針對AES加密解密演算法，我們提出了一個高效率的硬體架構，這個架構可以達到8 bits/cycle，Throughput為1000Mbps，相當於Pentium III 600Mhz的15倍，而且是NSA(美國國家安全局)提出的VHDL Model的2倍，我們的Gate Count為Pentium III 600Mhz的1/70倍，NSA VHDL Model的1/8倍。
    我們提出一個非常簡單的I/O Interface，以減低使用者負擔。將使用率極低的Key Schedule獨立出來，使得我們的設計更具有彈性，並且可以降低功率消耗。加入Pipeline Stage，增加了將近一倍的效能。為了晶片的可測性，也包含DFT的電路。

    晶片中包含一個ROM、十六個SBOX RAM、四個Key RAM。我們以Verilog完成所有設計，TimeMill Simulation的結果可以達到125Mhz，1000Mbps。最後，我們使用Compass cell library，以Apollo做Placement & Routing，在TSMC 0.35um SPTM CMOS製程來實作這個晶片。晶片面積為4.5x4.5mm2。

    We propose an efficient hardware architecture of the AES encryption/decryption algorithm. The architecture can achieve high-speed data transfer up to 8 bits/cycles, which is 15 times faster than a Pentium III 600. In our design, the I/O of the proposed architecture is reduced to 8 bits and the I/O port is serialized. It provides a simple and useful I/O interface for host. A better methodology of key schedule is involved. A pipeline stage doubles the performance. Besides, DFT is also considered. We have successfully implemented it using Compass cell library targeted at 0.35μm TSMC SPTM CMOS process. The die size of the chip is 4.5x4.5 mm2, and the maximum frequency is up to 125MHz. This AES cipher can be applied to such areas as a security for gigabit speed networks.

    Abstract i Contents ii List of Figures iv List of Tables v Chapter 1 Introduction 1 Chapter 2 Related Work 5 Chapter 3 AES Algorithm 9 3.1 Definition 9 3.1.1 Glossary of AES 9 3.1.2 Symbols of AES 10 3.2 Notation 12 3.2.1 Inputs, Outputs and Cipher Key 12 3.2.2 Array of Bytes 12 3.2.3 The State 13 3.3 Specification of AES Algorithm 14 3.3.1 Transformation Functions 14 3.3.2 Cipher 15 3.3.3 Key Expansion 16 3.3.4 Inverse Cipher 17 3.3.5 Equivalent Inverse Cipher 18 Chapter 4 Proposed Architecture 20 4.1 Serial Input/Output 20 4.2 Key Schedule 23 4.3 The Pipeline Architecture 26 4.4 Connected in Parallel 30 4.5 The Chip Interface 31 4.6 The System Configuration 33 4.6.1 Controller 34 4.6.2 Datapath 36 4.7 DFT consideration 37 Chapter 5 Design Flow and Strategy 38 5.1 Front-End 38 5.2 Back-End 39 Chapter 6 Experimental Results 40 6.1 Layout View and Chip Feature 40 6.2 Analysis 42 Chapter 7 Conclusions and Future Work 43 Bibliography 44

    [1] AES home page: http://www.nist.gov/aes/.
    [2] Joan Daemen and Vincent Rijmen, AES Proposal: Rijndael, AES Algorithm Submission, September 3, 1999, available at [1].
    [3] James Nechvatal, et al., Report on the Development of the Advanced Encryption Standard (AES), National Institute of Standards and Technology, October 2, 2000, available at [1].
    [4] Bryan Weeks, et al., Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms, National Security Agency white paper, May 15, 2000, available at [1].
    [5] Draft Federal Information Processing Standard (FIPS) for the Advanced Encryption Standard (AES), available at [1].
    [6] Federal Register: January 2, 1997 (Volume 62, Number 93), available at [1].
    [7] Federal Register: September 14, 1998 (Volume 63, Number 177), available at [1].
    [8] Federal Register: September 15, 1999 (Volume 64, Number 178), available at [1].
    [9] Will Wade, Encryption migrates to silicon as Net traffic swells, EE Times.
    [10] “HDL Compiler for Verilog Reference Manual Version 1998.02”, Synopsys, 1998.
    [11] “IC Layout Command Reference Manual, Release 1999.4”, Avanti, 1999.
    [12] “Dracula Reference Manual Version 4.5.1”, Cadence, 1997.
    [13] “Timemill Reference Manual Release 5.4”, EPIC, 2000.

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