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研究生： 張哲維
論文名稱： 具自我調變省電模式的低壓降線性穩壓器
Design of A Self-Modulation LDO for Power Saving
指導教授： 周懷樸
口試委員:
學位類別： 碩士
Master
系所名稱： 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年： 2007
畢業學年度： 96
語文別： 中文
論文頁數： 75
中文關鍵詞： 低壓降線性穩壓器 、低壓降穩壓器 、線性穩壓器
外文關鍵詞： LDO, Low Drop-Out Regulator
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    • 行動式通訊設備在應用上，系統狀態可依瞬間所需處理的資料量來區分成工作模式與待機模式。由於系統在這兩種的模式下性能要求十分不同，因此以傳統架構的低壓降線性穩壓器作直流對直流轉換，常無法同時達到系統所需高速應答特性與低電流消耗的要求。
    本論文就是針對傳統架構的低壓降線性穩壓器在此應用上的缺點所做的改善。提出一種可自動調變工作模式的低壓降穩壓器，以同時具有良好的暫態性能與低電流消耗設計目標。全電路使用TSMC 0.35um 2P4M的製程技術來設計與模擬分析，進一步規劃電路佈局並下線，取得晶片後作實際測試。晶片製作完成後，電路面積為628um x 694um。在供應電壓2V~5V的範圍內可穩定的產生1.87V的輸出電壓。在節能模式下，線性調節率為5.3mV/V，靜態電流約33uA；在高速模式下線性調節率為1.3mV/V、負載調節率為0.44mV/mA、靜態電流消耗約95uA；在暫態性能上，當負載電流從0至50mA瞬間增加，輸出端的電壓壓降約80mV，安定時間約為10us。

    目錄 誌謝..........................................................................................................Ⅰ 摘要..........................................................................................................Ⅱ 目錄..........................................................................................................Ⅲ 圖目錄......................................................................................................Ⅶ 表目錄......................................................................................................XI 第一章 緒論.............................................................................................1 1.1穩壓電路簡介..............................................................................1 1.1.1線性穩壓器..........................................................................1 1.1.2切換式穩壓器......................................................................3 1.1.3切換式電容穩壓器..............................................................4 1.2研究動機及目的..........................................................................5 1.3論文架構......................................................................................8 第二章 文獻回顧...................................................................................10 2.1低壓降線性穩壓器之架構與工作原理.....................................10 2.2低壓降線性穩壓器之規格簡介.................................................11 2.2.1線性調節率(Line Regulation) ...........................................11 2.2.2負載調節率(Load Regulation) .........................................12 2.2.3輸出電壓差(Dropout Voltage) .........................................14 2.2.4輸出準確率(Output Accuracy) .........................................14 2.2.5暫態響應(Transient Response) .........................................15 2.2.6靜態電流(Quiescent Current) ...........................................18 2.2.7轉換效率(Efficiency) ........................................................19 2.3具快速反應且低電流消耗之低壓降線性穩壓器...................19 2.3.1加入Current Efficiency Buffer的設計............................20 2.3.2加入Analog Driver的設計..............................................21 2.3.3動態回授偏壓電流(DNFB)技術......................................22 2.3.4加入數位控制偏壓電流(DCDB)電路的設計.................23 第三章 電路設計..................................................................................25 3.1電路運作流程與架構簡介.......................................................25 3.2規格設定...................................................................................27 3.3內部子電路設計.......................................................................28 3.3.1偏壓電路...........................................................................28 3.3.2參考電壓源.......................................................................29 3.3.3誤差放大器.......................................................................32 3.3.4輸出級電路.......................................................................33 3.3.5電流感測與模式切換電路...............................................34 第四章 模擬結果分析與討論..............................................................37 4.1偏壓電路與參考電壓源...........................................................37 4.1.1偏壓電路模擬分析...........................................................37 4.1.2參考電壓源模擬分析.......................................................38 4.2誤差放大器...............................................................................39 4.2.1 PS模式誤差放大器模擬分析........................................39 4.2.2 HS模式誤差放大器模擬分析........................................41 4.3電流感測與模式切換電路.......................................................44 4.4完整電路之模擬.......................................................................44 4.4.1 LDO操作於PS 模式下之模擬結果.............................44 4.4.2 LDO操作於HS 模式下之模擬結果.............................47 第五章 電路佈局、測試環境的規劃與實測......................................52 5.1佈局考量與技巧.........................................................................52 5.1.1差動電路對稱性問題.........................................................53 5.1.2電路中雜訊的隔離及寄生效應的降低.............................53 5.1.3電阻偏差問題.....................................................................54 5.2電路佈局.....................................................................................55 5.2.1誤差放大器佈局規劃.........................................................55 5.2.2電流感測與模式控制電路佈局規劃.................................57 5.2.3電阻佈局規劃.....................................................................58 5.2.4全電路佈局規.....................................................................59 5.3 量測環境與儀器........................................................................60 5.4 實測結果統計............................................................................62 5.4.1輸出電壓與供應電壓之關係.............................................62 5.4.2輸出電壓與負載電流之關係.............................................64 5.4.3靜態電流值與輸出負載電流之關係.................................64 5.4.4暫態響應.............................................................................65 第六章 結果討論與建議......................................................................71 6.1結果討論.....................................................................................71 6.2建議.............................................................................................72 參考文獻................................................................................................74

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    9. Chung-Wei Lin and Yen-Jen Liu, “A Power Efficient and Fast Transient Response Low Drop-Out Regulator in Standard CMOS Process”, 2006 International Symposium on VLSI Design, Automation and Test, pp. 1-4, April 2006

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