研究生: |
盧琮元 Lu, Tsung-Yuan |
---|---|
論文名稱: |
利用NO及N2O氧化後退火改善4H-SiC低壓三閘極金氧半場效電晶體特性及可靠度之研究 Study on Performance and Reliability of 4H-SiC Low Voltage Tri-Gate MOSFET with NO and N2O Post Oxidation Annealing |
指導教授: |
黃智方
Huang, Chih-Fang |
口試委員: |
吳添立
Wu, Tian-Li 趙得勝 Chao, Der-Sheng |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2022 |
畢業學年度: | 111 |
語文別: | 中文 |
論文頁數: | 62 |
中文關鍵詞: | 三閘極金氧半場效電晶體 、碳化矽 、氧化後退火 、可靠度 |
外文關鍵詞: | NO-anneling, sub-threshold-slope |
相關次數: | 點閱:1 下載:0 |
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傳統(0001)面的低壓SiC MOSFETs元件因為SiC/SiO2介面的高Dit,通道遷移率受到了限制,為了改善這個問題,本實驗提出了利用(112̅0)面側壁作為部分通道的tri-gate結構,並且分別使用NO、N2O進行氧化後退火降低Dit並比較他們帶來的影響。
本論文使用N型MOS capacitors、平面型MOSFETs、tri-gate MOSFETs來評估元件的特性以及氧化後退火的比較。跟N2O製程比起來NO製程(0001)面在距離傳導帶0.1 eV處的Dit值下降了約40 %,而且sub-threshold slope(S.S.)降低了20 %左右。Tri-gate結構的S.S.相比於平面結構也降低了約22 %,汲極飽和電流也大約是平面結構的兩倍。最後是初步的討論元件閘極氧化層可靠度,在適當的Vg ,max下, NO製程的tri-gate MOSFET不僅有著最佳的電流特性,而且不論是PBTI、NBTI都有著最小的ΔVTH,然而,在動態導通電阻的穩定性有觀察到一些問題。
Due to the high Dit at the SiC/SiO2 interface, the channel mobility of conventional (0001) face low-voltage SiC MOSFETs is limited. In order to improve this issue, this work proposes a tri-gate structure which include the (112̅0) face sidewall as part of the channel. In addition, NO and N2O are used for post-oxidation annealing to reduce the Dit and their effects are compared.
N-type MOS capacitors, planar MOSFETs, and tri-gate MOSFETs are used to evaluate the characteristics of devices and compare them with different post-oxidation annealing. Compared to the N2O process, the Dit¬ value for (0001) face of the NO process at E-EC=0.1 eV is reduced by about 40%, and the sub-threshold slope (S.S.) is reduced by about 20 %. Compared to the planar structure, the S.S. of tri-gate structure is also reduced by about 22 %, and the drain saturation current is about twice as large as the planar structure. Finally, the preliminary reliability of the gate oxide is discussed. Tri-gate MOSFET with NO process not only has the best current characteristics, but also has the smallest ΔVTH for both PBTI and NBTI under a reasonable Vg,max. However, some dynamic Ron issue is observed.
[1] T. Kimoto, "Material science and device physics in SiC technology for high-voltage power devices," Japanese Journal of Applied Physics, vol. 54, no. 4, p. 040103, 2015.
[2] A. R. Powell and L. B. Rowland, "SiC materials-progress, status, and potential roadblocks," Proceedings of the IEEE, vol. 90, no. 6, pp. 942-955, 2002.
[3] C.-M. Zetterling, Process technology for silicon carbide devices (no. 2). IET, 2002.
[4] T. Kimoto and J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons, 2014.
[5] H.-f. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, "Interfacial characteristics of N 2 O and NO nitrided SiO 2 grown on SiC by rapid thermal processing," Applied physics letters, vol. 70, no. 15, pp. 2028-2030, 1997.
[6] G. Chung et al., "Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide," IEEE Electron Device Letters, vol. 22, no. 4, pp. 176-178, 2001.
[7] T. Kimoto, Y. Kanzaki, M. Noborio, H. Kawano, and H. Matsunami, "Interface properties of metal–oxide–semiconductor structures on 4H-SiC {0001} and (1120) formed by N2O oxidation," Japanese journal of applied physics, vol. 44, no. 3R, p. 1213, 2005.
[8] H. Yano, T. Hirao, T. Kimoto, H. Matsunami, K. Asano, and Y. Sugawara, "High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~ 0) face," IEEE Electron Device Letters, vol. 20, no. 12, pp. 611-613, 1999.
[9] H. Yano, T. Kimoto, and H. Matsunami, "Shallow states at SiO 2/4 H-SiC interface on (1120) and (0001) faces," Applied physics letters, vol. 81, no. 2, pp. 301-303, 2002.
[10] R. Siemieniec et al., "A SiC trench MOSFET concept offering improved channel mobility and high reliability," in 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), 2017: IEEE, pp. P. 1-P. 13.
[11] R. P. Ramamurthy, N. Islam, M. Sampath, D. T. Morisette, and J. A. Cooper, "The tri-gate MOSFET: a new vertical power transistor in 4H-SiC," IEEE Electron Device Letters, vol. 42, no. 1, pp. 90-93, 2020.
[12] Y. Nanen, M. Kato, J. Suda, and T. Kimoto, "Effects of nitridation on 4H-SiC MOSFETs fabricated on various crystal faces," IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1260-1262, 2013.
[13] P. Fiorenza et al., "Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4H-SiC MOSFETs subjected to different nitridations," Applied Surface Science, vol. 557, p. 149752, 2021.
[14] D. K. Schroder, Semiconductor material and device characterization. John Wiley & Sons, 2015.
[15] A. Wadsworth, Ed. The Parametric Measurement Handbook 4th Edition. IEEE, 2018.
[16] J. Cooper, JA, "Advances in SiC MOS technology," physica status solidi (a), vol. 162, no. 1, pp. 305-320, 1997.
[17] D. A. Neamen, Semiconductor physics and devices: basic principles. McGraw-hill, 2003.
[18] A. V. Penumatcha, S. Swandono, and J. A. Cooper, "Limitations of the High-Low C-V Technique for MOS Interfaces With Large Time Constant Dispersion," IEEE transactions on electron devices, vol. 60, no. 3, pp. 923-926, 2013.
[19] V. Afanas’ ev, M. Bassler, G. Pensl, M. Schulz, and E. Stein von Kamienski, "Band offsets and electronic structure of SiC/SiO2 interfaces," Journal of Applied Physics, vol. 79, no. 6, pp. 3108-3114, 1996.
[20] R. Degraeve, B. Kaczer, and G. Groeseneken, "Degradation and breakdown in thin oxide layers: mechanisms, models and reliability prediction," Microelectronics Reliability, vol. 39, no. 10, pp. 1445-1460, 1999.
[21] J. Berens et al., "Similarities and differences of BTI in SiC and Si power MOSFETs," in 2020 IEEE International Reliability Physics Symposium (IRPS), 2020: IEEE, pp. 1-7.
[22] A. J. Lelis et al., "Time dependence of bias-stress-induced SiC MOSFET threshold-voltage instability measurements," IEEE transactions on Electron Devices, vol. 55, no. 8, pp. 1835-1840, 2008.
[23] A. J. Lelis, R. Green, D. B. Habersat, and M. El, "Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs," IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 316-323, 2014.
[24] A. Salinaro et al., "Charge pumping measurements on differently passivated lateral 4H-SiC MOSFETs," IEEE Transactions on Electron Devices, vol. 62, no. 1, pp. 155-163, 2014.
[25] M. Noborio, J. Suda, S. Beljakowa, M. Krieger, and T. Kimoto, "4H‐SiC MISFETs with nitrogen‐containing insulators," physica status solidi (a), vol. 206, no. 10, pp. 2374-2390, 2009.
[26] H. Yoshioka, J. Senzaki, A. Shimozato, Y. Tanaka, and H. Okumura, "N-channel field-effect mobility inversely proportional to the interface state density at the conduction band edges of SiO2/4H-SiC interfaces," AIP Advances, vol. 5, no. 1, p. 017109, 2015.
[27] K. Kutsuki et al., "Experimental investigation and modeling of inversion carrier effective mobility in 4H-SiC trench MOSFETs," Solid-State Electronics, vol. 157, pp. 12-19, 2019.
[28] S. Harada et al., "Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor," Journal of applied physics, vol. 91, no. 3, pp. 1568-1571, 2002.
[29] M. Noguchi, A. Koyama, T. Iwamatsu, H. Amishiro, H. Watanabe, and N. Miura, "Gate oxide instability and lifetime in SiC MOSFETs under a wide range of positive electric field stress," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020: IEEE, pp. 23.4. 1-23.4. 4.
[30] C.-T. Yen et al., "Negative bias temperature instability of SiC MOSFET induced by interface trap assisted hole trapping," Applied Physics Letters, vol. 108, no. 1, p. 012106, 2016.
[31] M. Noguchi, A. Koyama, T. Iwamatsu, H. Watanabe, and N. Miura, "Gate Oxide Instability against a Wide Range of Negative Electric Field Stress of SiC MOSFETs," in 2021 IEEE International Electron Devices Meeting (IEDM), 2021: IEEE, pp. 36.3. 1-36.3. 4.
[32] T. Kimoto, H. Yoshioka, and T. Nakamura, "Physics of SiC MOS interface and development of trench MOSFETs," in The 1st IEEE Workshop on Wide Bandgap Power Devices and Applications, 2013: IEEE, pp. 135-138.
[33] D. Peters, T. Aichinger, T. Basler, G. Rescher, K. Puschkarsky, and H. Reisinger, "Investigation of threshold voltage stability of SiC MOSFETs," in 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018: IEEE, pp. 40-43.
[34] G. Rescher, G. Pobegen, T. Aichinger, and T. Grasser, "On the subthreshold drain current sweep hysteresis of 4H-SiC nMOSFETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016: IEEE, pp. 10.8. 1-10.8. 4.
[35] M. Meneghini et al., "Reliability and failure analysis in power GaN-HEMTs: An overview," in 2017 IEEE International Reliability Physics Symposium (IRPS), 2017: IEEE, pp. 3B-2.1-3B-2.8.