高介電鈦酸鍶鋇閘極氧化層之研究及其在鐵電場效電晶體的應用

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研究生：	劉建宏 Chien Hung Liu
論文名稱：	高介電鈦酸鍶鋇閘極氧化層之研究及其在鐵電場效電晶體的應用 Study of (Ba0.5Sr0.5)TiO3 High-k Gate Dielectrics and Its Application on Ferroelectric Field Effect Transistors
指導教授：	吳振名 Jenn Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	144
中文關鍵詞：	鈦酸鍶鋇、氮化、鐵電記憶體
外文關鍵詞：	High-k, BST, Nitridation, FeRAM, MFIS, LiNbO3
相關次數：	點閱：2 下載：0
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眾多high-k材料中，鈦酸鍶鋇(BST)因具有高介電常數，高崩潰電壓及低漏電流，被視為下一世代G-bits DRAM的關鍵材料，同時也是未來電晶體閘極氧化層的候選者之一。近年來，鐵電場效電晶體(非揮發性記憶體:1- Transistor type FeRAM)因具有非破壞式讀取以及超高儲存密度等優點，因此受到各界矚目。而鈦酸鍶鋇因其鈣鈦礦結構和高介電常數的特性，非常有利於成長高品質的鐵電薄膜以及實現低電壓操作的鐵電場效記憶體。
本論文主要分為三個主題: 其一，利用射頻磁控濺鍍法在p-type Si(100)基板上沉積BST 薄膜，探討厚度效應、濺鍍氣氛、工作壓力及RTA時間等製程參數對薄膜結晶性質及電性表現的影響。其二，在沉積薄膜前，導入N2O氮化製程來抑制BST與矽之間所產生的界面層厚度，實驗結果發現經N2O氮化前處理的BST試片有較高的整體電容值，且漏電流密度在-1MV/cm可降低至3*10-9A/cm2。此外在崩潰電場、界面態密度、遲滯現象等可靠度測試上也有明顯的改善。
最後，我們應用經過氮化前處理的BST薄膜作為金屬-鐵電膜-絕緣層-矽(MFIS)的鐵電場效電晶體的絕緣層，以鋯酸鉛鋇(Pb1-xBaxZrO3, PBZ)以及鈮酸鋰(LiNbO3,LNO)為鐵電層，製作成MFIS電容結構並探討其記憶特性。
以Pt/PBZ/BST/Si MFIS電容結構而言，應用BST薄膜做為MFIS的緩衝絕緣層，可以有效壓抑漏電流以及促進PBZ薄膜(200)優選指向的成長。在掃描振幅電壓±5V時可得到1.76V的記憶視窗，已足夠運用於記憶元件的邏輯偵測。而對於Pt/ LiNbO3/BST/Si MFIS電容結構來說，LiNbO3 雖然無法在BST薄膜上成長出c-軸(006)的優選指向，但是比起Pt/LiNbO3/Si MFS電容結構而言，仍可大幅降低其漏電流密度；其記憶視窗隨著掃描振幅電壓由±3V增至±14V時，亦從0.7V增加到3.96V。此外，載子注入及捕陷效應對MFIS記憶特性的影響在論文中也作了研究和探討。

Contents

Abstract…………………………………………………………………I
Acknowledgements……………………………………………………III
Contents………………………………………………………………..IV
List of tables……………………………………………………………IX
List of figures……………………………………………………………X


Chapter 1 Introduction:
Application of Ferroelectric Materials on Semiconductor Device…...1
    1.1 High-k gate dielectrics……………………………………………………...1
    1.2 Ferroelectric Random Access Memory (FeRAM)………………………...4
    1.3 Motivation…………………………………………………………………...6
    1.4 Thesis organization…………………………………………………………7

Chapter 2 Literature Review………………………………………… 13
2.1 Dielectric behavior…………………………………………………...........13
2.1.1 Polarization…………………………………………………………13
2.1.2 Dielectric Constant and Dielectric Loss…………………………..14
2.1.3 Dielectric breakdown………………………………........................14
2.1.4 Leakage current mechanism………………………........................15
2-2 Ferroelectricity……………………………………………………….........16
2-3 Ferroelectric Field Effect Transistors (1-Transistor type FeRAM)……18
2.3.1 Type of 1-T type FeRAM…………………………………………..19
2.3.2 Operation Principle of 1-T type FeRAM…………………………21
2.3.3 The current bottleneck of 1-T type FeRAM………………….......22
2.4 The issue of high-k gate dielectric as insulating buffer layer………….. 25
2.5 Nitridation treatment for high-k gate dielectrics………………………..28
2.5.1 Introduction………………………………………………………...28
2.5.2 Methods and mechanisms of nitridation for silicon……………...29
2.6 Characteristic of (BaxSr1-x)TiO3 (BST) materials………………………. 30
2.7 Characteristic of (Pb1-xBax) ZrO3 (PBZ) materials……………………...31
2.8 Characteristic of LiNbO3 (LNO) materials………………………………32

Chapter 3 Experimental procedure…………………………………..51
3.1 Preparation of BST thin films…………………………………………….51
3.1.1 Fabrication of BST Targets………………………………………..51
3.1.2 Preparation of Substrates …………………………………………51
3.1.3 Fabrication of Pt/BST/Si MIS and Pt/BST/Pt MIM Capacitors...53
3.2 Fabrication of Pt/PBZ/BST/Si MFIS Capacitors………………………..53
3.2.1 Fabrication of PBZ Targets………………………………………..53
3.2.2 Fabrication of Pt/PBZ/Pt MFM Capacitors and Pt/PBZ/BST/Si MFIS Capacitors…………………………………………………...53
3.3 Fabrication of Pt/LiNbO3/BST/Si MFIS Capacitors…………………….53
3.3.1 Fabrication of LiNbO3 Targets……………………………………53
3.2.2 Fabrication of Pt/LiNbO3/Pt (MFM), Pt/LiNbO3/Si(MFS) , and Pt/ LiNbO3/BST/Si (MFIS) Capacitors……………………………..54
3.4 Physical Measurement…………………………………………………….54
3.4.1 Ellipsometry………………………………………………………...54
3.4.2 X-Ray Diffraction (XRD)…………………………………………..54
3.4.3 X-ray photoelectron spectrometer (XPS)…………………………55
3.4.4 Auger electron spectroscopy (AES)……………………………….55
3.4.5 Atomic force microscopy (AFM) ………………………………….55
3.4.6 Scanning Electron Microscopy (SEM)……………………………55
3.5 Electrical Measurement …………………………………………………..56
3.5.1 Capacitance-Voltage (C-V) Measurements……………………….56
3.5.2 Ferroelectricity (P-E) Measurement………………………………56
3.5.3 Current – Voltage (I-V) Measurement……………………………56

Chapter 4 Study of the characteristics of BST high-k gate dielectrics………………………………………………...65
4-1 Effect of film thickness……………………………………………………65
4-1.1 X ray diffraction analysis………………………………………….65
4-1.2 Surface morphology………………………………………………..65
4-1.3 Electrical properties………………………………………………..66
4-2 Effect of Ar/O2 ratio……………………………………………………….67
4-2.1 X ray diffraction analysis………………………………………….68
4-2.2 Surface morphology………………………………………………..68
4-2.3 Electrical properties………………………………………………..69
4-3 Effect of working pressure………………………………………………..70
4-3.1 X ray analysis……………………………………………………....70
4-3.2 Composition analysis………………………………………………71
4-3.3 Electrical analysis…………………………………………………..71
4-4 Nitridation pre-treatment ………………………………………………...73
4-4.1 Comparison of electrical properties………………………………73
4-4.2 Comparison of reliability issues…………………………………...75
4-5 RTA treatment…………………………………………………………….77
4-5.1 X ray analysis………………………………………………………78
4-5.2 Electrical analysis ………………………………………………….78

Chapter 5 Study and Fabrication of MFIS Capacitors……………...99
5.1 (Pb,Ba)ZrO3 thin films………………………………………………… …99
5.1.1 Ferroelectricity of PBZ thin films…………………………………99
5.1.2 Structure properties of PBZ thin films deposited on BST…….....99
5.1.3 Electrical and memory properties of Pt/PBZ/BST/Si MFIS capacitors…………………………………………………………100
5.1.4 AES depth profiles of PBZ/BST/Si stakes……………………….103
5.2 LiNbO3 thin films………………………………………………………...104
5.2.1 Fabrication and structure properties of LiNbO3 thin films……104
5.2.2 Ferroelectricity of LiNbO3 thin films……………………………106
5.2.3 Electrical and memory properties of Pt/LiNbO3(LNO)/BST/Si MFIS capacitors………………………………………………….107

Chapter 6 Conclusions……………………………………………….123

Reference……………………………………………………………...126


List of tables
Table 1-1. Dielectric constant of various high-k materials……………………….10
Table 1-2. Comparison of features of FRAM and other memory devices……….11
Table 2-1. The J-E relations of leakage current mechanisms……………………38
Table 2-2. The cell size factor of 1-T FeRAM and capacitor type FeRAM……..43
Table 2-3. Basic properties of LiNbO3 crystal…………………………………… 49
Table 3.1. The RF magnetron sputtering system………………………………....59
Table 3-2. Sputtering parameters of BST thin films deposition………………….60
Table 3-3. Sputtering parameters of Pt top electrodes……………………………60
Table 3-4. Sputtering parameters of PBZ thin films deposition………………....64
Table 3-5. Sputtering parameters of LiNbO3 thin films deposition……………...64
Table5-1. Deposition conditions of LiNbO3 thin films on p-Si (100) substrates..115







List of figures
Fig.1-1.International Technology Roadmap for Semiconductors (ITRS 2004)……………………………………………………………………........9
Fig.1-2. LOP Logic Scaling-up of Gate Leakage Current Density Limit and of Simulated Gate Leakage due to Direct Tunneling. (ITRS 2004)…….....9
Fig.1-3. The technology requirements of FeRAM. (ITRS 2004 Updated)……....12
Fig.1-4. (a) 1T-1C type FeRAM (b) 1-T type FeRAM…........................................12
Fig.2-1. Four kinds of polarization mechanisms.....................................................35
Fig.2-2. The relation of the response frequency and polarization mechanisms...36
Fig.2-3. The phase difference of current and voltage in circuits………………...36
Fig.2-4. The MIS band diagram of Schottky emission……………………………37
Fig.2-5. The MIS band diagram of (a) F-N tunneling (b) Direct tunneling……..37
Fig.2-6. The MIS band diagram of Pool-Frenkel emission………………………38
Fig.2-7.The origin of ferroelectricity: Dipole created by the relative displacement
of the sublattices of the cations and oxygen………………………….......39
Fig.2-8. The perovskite structure of BaTiO3……………………………………...39
Fig.2-9. The typical hysteresis loop (polarization to electric field) of ferroelectric materials……………………………………………………………………40
Fig.2-10. The two stable polarization state of ferroelectric materials like PZT can be defined as “0” and “1” for 1T-1C type FeRAM…………………..41
Fig.2-11. Type of 1T-FeRAM: (a) MFS-FET (b) MFIS-FET (c) MFMIS-FET..41
Fig.2-12. Schematic diagram of an all-perovskite ferroelectric FET and
measurement circuit……………………………………………………...41
Fig.2-13. Schematic of memory cell for 1T2C-type FET and polarization
directions for binary data………………………………………………..42
Fig.2-14. Operation of 1-T FeRAM and the memory window characteristic…...43
Fig.2-15. Gate stack of the 1T-FeRAM is modeled by a ferroelectric capacitance
(CF ) in series with the semiconductor capacitance CIS ………………..43
Fig.2-16. Schematic for the effect of gate leakage current on 1-T FeRAM……..44
Fig.2-17. The location of the defect and trap charge in the MIS structure……...44
Fig.2-18. The effect of fixed charge on the flat band voltage shift……………….45
Fig.2-19. The charge trapping into the oxide cause C-V hysteresis loop……......45
Fig.2-20. The starching out effect caused by interface trap……………………...45
Fig.2-21.The mobile ions drift cause the counterclockwise C-V hysteresis……..45
Fig.2-22. Schematic model for silicon oxynitridation for NO or N2O…………...46
Fig.2-23. Nitrogen distribution profile for different nitridation sequence…........46
Fig.2-24. Effect of several isovalent substitutions on transition temperatures of ceramic BaTiO3………………………………………………………………………. ………………..47
Fig.2-25. The phase diagram of (Pb-Ba)ZrO3 ceramics. Aα is antiferroelectric
phase, Fα is ferroelectric phase, and P is paraelectric phase………….48
Fig.2-26. The relation of phase change, composition change and temperature...49
Fig.2-27. Structure of LiNbO3 ………………………………………………………………………………...49
Fig.2-28. Cation arrangement in LiNbO3, showing orientation of dipole between
Li +and Nb5+   …………………………………………………………………………………………..50
Fig.2-29. Li2O-Nb2O5 phase diagram near the existence of LiNbO3 …….......................50
Fig.3-1. The preparation flow chart of BST targets………………………………58
Fig.3-2. The 1-step cleaning process of silicon substrates………………………...59
Fig.3-3. The flow chart of the BST metal/insulator/silicon (MIS) capacitors and
PBZ or LiNbO3 based MFIS capacitors preparation…………………...61
Fig.3-4. The preparation flow chart of PBZ targets……………………………....62
Fig.3-5. The preparation flow chart of LiNbO3 targets…………………………..63
Fig.4-1. XRD spectra of BST deposited on silicon with various thicknesses……80
Fig.4-2. AFM images of BST surface morphology with various thickness:
(a) 70nm (b) 50nm(c) 30nm (d) 20nm…………………………………….80
Fig.4-3. High frequency C-V curve of BST MIS capacitors with various
thicknesses………………………………………………………………… 82
Fig.4-4. Dielectric constant and EOT of BST MIS capacitors with various
thicknesses………………………………………………………………….83
Fig.4-5. Leakage current density of BST MIS capacitors with various
thicknesses………………………………………………………………….83
Fig.4-6. Deposition rate with different oxygen ambient of sputtering BST thin films……………………………………………………………………….84
Fig.4-7. XRD spectra of 30nm BST deposited on silicon with various Ar/O2 ratios………………………………………………………………………84
Fig.4-8. AFM images of BST surface morphology with various Ar/O2 ratios:
(a) 90/10  (b) 80/20  (c) 70/30  (d) 60/40……………………………..86
Fig.4-9. The dielectric constant of 30nm BST thin films deposited on Pt bottom electrodes with various Ar/O2 ratios…………………………………….87
Fig.4-10. High frequency C-V curve of 30nm BST MIS capacitors with various Ar/O2 ratios………………………………………………………………87
Fig.4-11. Dielectric constant and EOT of BST MIS capacitors with various Ar/O2 ratios……………………………………………………………………..88
Fig.4-12. Leakage current density of BST thin films deposited in various Ar/O2 ratios……………………………………………………………………..88
Fig.4-13. Deposition rate of BST thin films deposited in various working
pressure………………………………………………………………….89
Fig.4-14. XRD spectra of 30nm BST deposited on silicon with various working
pressure……………………………………………………………….....89
Fig.4-15. XPS composition analysis: (Ba+Sr)/Ti ratios of BST thin films deposited by various working pressure……………………………..90
Fig.4-16. High frequency C-V curve of 30nm BST MIS capacitors with various
workingpressure………………………………………………………..90
Fig.4-17. The dissipation factors of BST MIS capacitors with various working
pressure………………………………………………………………….91
Fig.4-18. XPS of the N2O pre-treatment silicon surface………………………...91
Fig.4-19. High frequency C-V curves of N2O pre-treatment samples and
non-nitridation samples………………………………………………...92
Fig.4-20. AES depth profiles of (a) non-nitrided samples (b) N2O pre-treatment
samples…………………………………………………………………..92
Fig.4-21. The leakage current density of N2O pre-treatment samples and N2O
pre-treatment samples and non-nitrided samples……………………93
Fig.4-22. The high-frequency C-V hysteresis of N2O pre-treatment samples and
non-nitrided samples…………………………………………………....94
Fig.4-23. Interface traps density of (a) non-nitrided samples and (b) N2O
pre-treatment samples………………………………………………......94
Fig.4-24. The time zero dielectric breakdown measurements of N2O
pre-treatment samples and non-nitrided samples…………………….95
Fig.4-25. TDDB life time test of N2O pre-treatment samples and non-nitrided
samples…………………………………………………………………..95
Fig.4-26. XRD spectra of BST thin films at RTA 600˚C, O2 ambient with
different time…………………………………………………………….96
Fig.4-27. High frequency C-V curves of BST thin films at RTA 600˚C, O2 ambient
with different time………………………………………………………97
Fig.4-28. Dielectric constant and EOT of BST thin films at RTA 600˚C, O2
ambient with different time…………………………………………… 97
Fig.4-29. Leakage current of BST thin films at RTA 600˚C, O2 ambient with
different time…………………………………………………………….97
Fig.4-30. Interface trap density (Dit) of BST thin films at RTA 600˚C, O2 ambient
with different time………………………………………………………98
Fig.5-1. XRD spectra of PBZ thin films deposited on Pt bottom electrode…….110
Fig.5-2. P-E curve of PBZ thin films with 360nm thicknesses deposited on Pt
electrode…………………………………………………………………..110
Fig.5-3. XRD spectra of PBZ thin films deposited on silicon with 30nm BST
buffer layer……………………………………………………………….111
Fig.5-4. SEM image of PBZ thin films deposited on BST (30nm)/Si substrates
(a) Cross section (b) plane view…………………………………………111
Fig.5-5. AFM image of of PBZ thin films deposited on BST (30nm)/Si substrates
(a) Surface morphology (b) top view……………………………………112
Fig.5-6. High frequency C-V curve of Pt/PBZ(360nm)/ BST(30nm)/Si MFIS
capacitors ………………………………………………………………...112
Fig. 5-7. Unstable flat band voltage shift of Pt/PBZ(360nm)/ BST(30nm)/Si MFIS
capacitors when the applied gate voltages are larger than 5V……….113
Fig .5-8. The relationship of memory windows with increasing sweep gate
bias……………………………………………………………………….113
Fig.5-9. Leakage current density of Pt/PBZ(360nm)/ BST(30nm)/Si MFIS
capacitors…………………………………………………………………114
Fig.5-10. The retention characteristics of Pt/PBZ(360nm)/ BST(30nm)/Si MFIS
capacitors………………………………………………………………..114
Fig.5-11. AES depth profiles of PBZ(360nm)/BST(30nm)/Si stakes……………115
Fig.5-12. XRD spectra of LiNbO3 thin films deposited on silicon substrates with
optimized condition : Ar/O2 = 60/40, 2mtorr, 90W, 600ﾟC…………116
Fig.5-13. XRD spectra of LiNbO3 thin films deposited on Pt substrates with
optimized condition : Ar/O2 = 60/40, 2mtorr, 90W, 600ﾟC…………132
Fig.5-14. SEM images of 160nm thick LiNbO3 thin films deposited on silicon
substrates. (a) plane view (b) cross section……………………………116
Fig.5-15. SEM plane view of 160nm thick LiNbO3 thin films deposited on Pt
substrates………………………………………………………………...117
Fig.5-16. XRD spectra of LiNbO3 thin films deposited on silicon substrates with 30nm thick BST buffer layer. (Optimized condition : Ar/O2 = 80/20, 2mtorr, 90W, 600ﾟC.)…………………………………………………..118
Fig.5-17. SEM plane view of LiNbO3 thin films deposited on silicon substrates with 30nm BST buffer layers………………………………………….118
Fig.5.18. AFM images of LiNbO3 thin films deposited on silicon substrates with 30nm BST buffer layers………………………………………………...119
Fig.5.19. P-E curves of 160nm thick LiNbO3 thin films deposited on silicon
substrates………………………………………………………………….119
Fig.5-20. Leakage current density of Pt/ LiNbO3(160nm)/Si capacitors……….120
Fig.5-21. High frequency C-V curve of Pt/LNO (160nm)/ BST (30nm)/Si MFIS
capacitors with the sweep gate bias ±3 ~ ±8V…………………………120
Fig.5-22. High frequency C-V curve of Pt/LNO (160nm)/ BST (30nm)/Si MFIS
capacitors with the sweep gate bias ±9 ~ ±15V………………………..121
Fig.5-23. High frequency C-V curve of Pt/LNO (160nm)/ BST (30nm)/Si MFIS
capacitors with different scan rate; the sweep gate bias is ±5V……...121
Fig.5-24. The relationship of memory windows with increasing sweep gate bias
on Pt/LNO (160nm)/ BST (30nm)/Si MFIS capacitors….....................122
Fig.5-25. Leakage current density of Pt/LNO (160nm)/ BST (30nm)/Si MFIS
capacitors………………………………………………………………122

                                

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