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研究生: 林欣逸
Lin, Hsin-Yi
論文名稱: 電荷儲存式的鰭式奈米線穿隧電晶體非揮發性記憶體之研究
Study of Fin-shaped Nanowires Tunneling-Field-Effect-Transistor Charge Trapping Nonvolatile Memory
指導教授: 吳永俊
Wu, Yung-Chun
口試委員: 李敏鴻
Lee, Min-Hung
羅廣禮
Luo, Guang-Li
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 66
中文關鍵詞: 非揮發性記憶體薄膜電晶體穿隧電晶體奈米線電荷儲存式鰭式
外文關鍵詞: Nonvolatile Memory (NVM), Thin Film Transistor (TFT), Tunneling-Field-Effect-Transistor (TFET), Nanowire (NW), Charge Trapping (CT), Fin-shaped
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  • 具全寫入機制電荷儲存式的鰭式複晶矽奈米線穿隧電晶體非揮發性記憶體是第一次被研究實現,且可以展現大的記憶窗以及優質的可靠度。
    鰭式奈米線架構可提供快速的寫入/抹除操作。除此之外,電荷離散儲存式架構也更加優化可靠度特性。不僅如此,由於具有複晶矽形成之通道,使本研究有機會應用於未來高密度三維堆疊的非揮發性記憶體領域。
    在FN tunneling寫入的情形下,所有的操作機制包含傳導電流機制和記憶體寫入/抹除機制全部都建立於量子穿隧傳輸,並且擁有不錯的記憶窗(在Vg = 17V, tp = 1ms條件下,記憶窗可達4.75V),以及優秀的88 %忍耐度和處於85 oC高溫的惡劣環境下維持65 %儲存10年的能力。在CHE寫入的情形下,本研究可展現大的記憶窗(在Vg = 8V, Vd = 6V, tp = 1ms條件下,記憶窗可達4V),以及不錯的74 %忍耐度。更重要的是處於85 oC高溫的惡劣環境下,可維持極好81 %的儲存10年能力。在BBHE寫入的情形下,本研究利用極低寫入電壓條件即可展現極大的記憶窗(在Vg = 3V, Vd =-6V, tp = 1ms小電壓條件下,記憶窗即可達4V),以及不錯的74 %忍耐度和處於85 oC高溫的惡劣環境下維持63 %的儲存10年能力。
    根據上述所提到的描述,電荷儲存式的鰭式奈米線穿隧電晶體非揮發性記憶體擁有低靜態功率消耗和低寫入電壓特性,所以非常有潛力被應用於未來高密度三維堆疊的手持式產品之中。


    The Pi-gate polycrystalline silicon (poly-Si) nanowires tunneling field effect transistor (TFET) charge trapping(CT) nonvolatile memory (NVM) with all programming mechanisms and shows a large memory window and good reliability is demonstrated for the first time.
    Pi-gate nanowires structure performs faster program/erase speed. Otherwise, the SONOS-type structure can improve excellent reliability. Furthermore, due to the poly-Si channel technology, it is possible to develop in 3D high-density stacked NVM.
    In FN tunneling programming, operation of conducting current and program/erase are based on all quantum tunneling transportation. Pi-gate T-SONOS NVM generates a large memory window (ΔVth=4.75V at Vg = 17V, tp = 1ms) and excellent reliability of 88 % endurance behavior after 10k P/E cycles and 65 % retained ability for ten years at 85 oC. In CHE programming, Pi-gate T-SONOS NVM presents a large memory window (ΔVth=4V at Vg=8V, Vd=6V, tp=1ms), and 74 % endurance behavior after 10k P/E cycles. Moreover, a superior 81 % retention behavior for ten years at 85 oC is presented. In BBHE programming, Pi-gate T-SONOS NVM performs a high programming efficiency, larger memory window (ΔVth=4V at Vg=3V, Vs=-6V, tp=1ms), excellent reliability of 74 % endurance after 10k P/E cycles and 63 % retention for ten years at 85 oC can be achieved.
    Based on above-mentioned description, Pi-gate nanowires T-SONOS NVM is suitable to use in future 3D high-density embedded portable applications with low stand-by power consumption and ultra low program voltage.

    中 文 摘 要 i Abstract iii Acknowledge v Contents vii Table Captions x Figure Captions xi Chapter 1 Introduction 1 1.1 Tunneling-Field-Effect-transistor (TFET) 1 1.2 Introduction of Nonvolatile Memory 3 1.2.1 Historical Perspective to Nonvolatile Memory 3 1.2.2 The SONOS NVM 5 1.3 The Multi-Gate Structure with nanowires 6 1.4 The 3D development of Poly-Si Channel 7 1.5 Motivation 8 1.6 Thesis Organization 9 Chapter 2 Basic Mechanisms and Reliability of Nonvolatile Memory 17 2.1 Basic Mechanisms of Nonvolatile Memory 17 2.1.1 Introduction 17 2.1.2 Program Mechanism 17 2.1.2.1 Fowler-Nordheim (FN) Tunneling 17 2.1.2.2 Channel Hot-Electron (CHE) Injection 18 2.1.2.3 Band-To-Band Tunneling Induced Hot Electron (BBHE) Injection 19 2.1.3 Erase Mechanism 20 2.1.3.1 Fowler-Nordheim (FN) Tunneling 20 2.1.3.2 Edge Fowler-Nordheim (FN) Tunneling 20 2.1.4 Program/Erase Speed 21 2.2 Basic Reliability of Nonvolatile Memory 21 2.2.1 Endurance 21 2.2.2 Retention 21 Chapter 3 Device Fabrication and Simulation 32 3.1 Device Structure and Fabrication 32 3.2 Simulation of Pi-gate Structure 33 Chapter 4 Characteristics of Pi-gate Nanowires Tunnel-FET SONOS Nonvolatile Memory with All Programming Mechanisms 41 4.1 Introduction 41 4.2 FN-Tunneling Programming 42 4.2.1 Simulation of FN-Tunneling Mechanism Band Diagram 42 4.2.2 Id-Vg Characteristic 42 4.2.3 Program/Erase Characteristics 43 4.2.4 Reliability of Data Endurance 44 4.2.5 Reliability of Data Retention 44 4.3 Channel Hot-Electron (CHE) Injection Programming 48 4.3.1 Id-Vg Characteristic 48 4.3.2 Program/Erase Characteristics 48 4.3.3 Reliability of Data Endurance 49 4.3.4 Reliability of Data Retention 49 4.4 Band-To-Band Tunneling Induced Hot Electron (BBHE) Injection Programming 53 4.4.1 Simulation of BBHE Mechanism Band Diagram 53 4.4.2 Id-Vg characteristic 53 4.4.3 Program/Erase characteristics 54 4.4.4 Reliability of Data Endurance 54 4.4.5 Reliability of Data Retention 55 4.5 Performance Comparison of Pi-gate T-SONOS NVM with FN-tunneling, CHE and BBHE Program Mechanisms 59 Chapter 5 Conclusion 61 Reference 62

    Chapter 1

    [1-1] International Technology Roadmap for Semiconductors (ITRS), 2011, (http://www.itrs.net/Links/2011ITRS/Home2011.htm)
    [1-3] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface”, Tech. Dig. - Int. Electron Devices Meet. 2006, 1.
    [1-4] A. J. Walker, S. Nallamothu, E. H. Chen, M. Mahajani, S.B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V.L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, Tech. Dig. VLSI Technol. Symp. 2003, 29.
    [1-5] Adrian M. Ionescu, Heike Riel “Tunnel field-effect transistors as energy efficient electronic switches”, 17 NOVEMBER 2011, VOL 479, NATURE, 329
    [1-6] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Tunnel field-effect transistor without gate-drain overlap”, Appl. Phys. Lett. 91, 053102 2007.
    [1-7] M. T. Björk, J. Knoch, H. Schmid, H. Riel, and W. Riess, “Silicon nanowire tunneling field-effect transistors”, Appl. Phys. Lett. 92, 193504, 2008.
    [1-8] C. Anghel, P. Chilagani, A. Amara, and A. Vladimirescu, “Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric”, Appl. Phys. Lett. 96, 122104, 2010.
    [1-9] S. Cho, I. M. Kang, T. I. Kamins, B.-G. Park, and J. S. Harris, “Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation”, Appl. Phys. Lett. 99, 243505, 2011.
    [1-10] W. G. Vandenberghe, A. S. Verhulst, K.-H. Kao, K. D. Meyer, B. Sorée, W. Magnus, and G. Groeseneken, “A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors”, Appl. Phys. Lett. 100, 193509, 2012.
    [1-11] M. Schmidt, R. A. Minamisawa, S. Richter, A. Schafer, D. Buca, J. M. Hartmann, Q.-T. Zhao, and S. Mantl, “Unipolar behavior of asymmetrically doped strained Si0.5Ge0.5 tunneling field-effect transistors”, Appl. Phys. Lett. 101, 123501, 2012.
    [1-12] K. Jeon, W. Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H. H. Tseng, R. Jammy, T. J. King Liu, and C. Hu, “Si Tunnel Transistors with a Novel Silicided Source and 46mV/dec Swing”, Tech. Dig. VLSI Technol. Symp. 2010, 121.
    [1-13] W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec”, IEEE Electron Device Lett. 28, 743, 2007.
    [1-14] J. Knoch, S. Mantl, J. Appenzeller, “Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices”, Solid-State Electronics. 51, 572, 2007.
    [1-15] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, C. C. Ko, S. Yang., L. W. Feng, S. M, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications”, Appl. Phys. Lett.2007
    [1-16] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti “Introduction to Flash Memory”, Proc. IEEE 91, 489–502, 2003.
    [1-17] K. Kahng and S. Sze, “A floating gate and its application to memory devices”, IEEE Transactions on Electron Devices, vol. 14, pp. 629-629, 1967.
    [1-18] Frohman-Bentchkowsky, D.FAMOS, “A new semiconductor charge storage device”, Solid State Electronics. 17,517. 1974.
    [1-19] Harari E., Schmitz L., Troutman B., and Wang S., “A 256 bit nonovolatile static RAM”, IEEE ISSCC Tech. Dig., pp. 152, 1978..
    [1-20] Kynett V.N., Baker A., Frandrich M., Hoekstra G.,Jungroth O., Kreifels J., and Wells S., “An in-system reprogrammable 256K CMOS Flash memory”, ISSCC Tec. Dig., pp.132, 1988.
    [1-21] Barbara De Salvo, Cosimo Gerardi, Rob van Schaijk, Salvatore A. Lombardo, Domenico Corso, Cristina Plantamura, Stella Serafino, Giuseppe Ammendola, Michiel van Duuren, Pierre Goarin, Wan Yuet Mei, Kees van der Jeugd, Thierry Baron, Marc Gély, Pierre Mur, and Simon Deleonibus, “Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, SEPTEMBER 2004
    [1-22] www.intel.com/technology/architecture-silicon/22nm/
    [1-23] N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications”, IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov 2008.
    [1-24] C. Hu, “Modern Semiconductor Devices for Integrated Circuit”, (Prentice Hall, New Jersey, 2008), pp. 299-300.
    [1-25] M. Bohr, “The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era”, IEDM Tech. Dig., 2011, pp. 1-6.
    [1-26] Jean-Pierre Colinge, Anantha Chandrakasan, “FinFETs and Other Multi-Gate Transistors”, ch 1, Springer, 2007, p.22
    [1-27] H.Tanaka, M.Kido, K.Yahashi, et al. “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, VLSI, pp.14 – 15, 2007

    Chapter 2

    [2-1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, Proceedings of IEEE, Vol. 85, pp. 1248, 1997.
    [2-2] Tseung-Yuen Tseng, Simon Min Sze, “NONVOLATILE MEMORIES”, AMERICAN SCIENTIFIC PUBLISHERS, p38-39
    [2-3] M. Lenzlinger and E. H. Snow, J. Appl. Phys. 40, 278, 1969.
    [2-4] Z. T. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49, 1606, 2002.
    [2-5] M. H. White, Y. Yang, A Purwar, and M. L. French, IEEE Trans. Compon., Packag., Manuf Techno!. A 20, 190, 1997.
    [2-6] M. She, “Semiconductor Flash Memory Scaling”, Ph.D. Thesis, University of California at Berkeley, 2003.
    [2-7] Simon Tam, Ko, P.-K, Chenming Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 9, SEPTEMBER 1984
    [2-8] T. Ohnakado , K. Mitsunaga , M. Nunoshita , H. Onoda , K. Sakakibara , N. Tsuji , N. Ajika , M. Hatanaka , and H. Miyoshi , “Novel Electron Injection Method Using Band - to – Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a p - Channel Cell”, IEDM Tech. Dig ., pp. 279 – 282 , 1995 .
    [2-9] T.Y.Chan, J.Chen, P.K.Ko and C.Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” IEDM Tech. Dig., 1987, p.718
    [2-10] C.Chang and J.Lien, “CORNER-FIELD INDUCED DRAIN LEAKAGE IN THIN OXIDE MOSFETS”, IEDM Tech. Dig., 1987, p.714
    [2-11] Takahiro Ohnakado, Hiroshi Onoda, Osamu Sakamoto, Kiyoshi Hayashi, Naho Nishioka, Hiroshi Takada, Kazuyuki Sugahara, Natsuo Ajika, and Shin-ichi Satoh, “Device characteristics of 0.35 μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE TED, VOL. 46, NO. 9, SEPTEMBER 1999

    Chapter 3

    [3-1] Sentaurus TCAD, 2011 Synopsys.

    Chapter 4

    [4-1] Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan Jang, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Kihyun Kim, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang, Jong-Wook Lee, Yong-Hoon Son, U-In Chung, Won-Seong Lee, “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory”, VLSI dig., 2009, p.192.
    [4-2] Erh-Kun Lai, Hang-Ting Lue, Yi-Hsuan Hsiao, Jung-Yu Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, +Jeng Gong, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, IEDM tech. dig, 2006.
    [4-3] Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device” VLSI, 2010, p.131.

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