半導體產業乃為資本與技術高度密集的產業，且具有高成本與上市時間的壓力，如何提升良率皆是半導體產業不容小覷的課題。在實際產線上，晶圓圖乃提供追查晶片發生異常的重要線索，建構辨識故障系統可找出可能產生低良率的原因，目前國內晶圓廠對於晶圓圖的圖像辨識大多是以人工目視的方式來進行，但由於晶圓圖分佈的情況雜亂，且可能因為工程師本身的經驗和主觀判斷因素造成辨識時間過長與準確性的不足，影響問題解決的效率。本研究考慮不同缺陷差異組合影響的程度以及過濾雜訊等資料前置處理，並結合類神經網路中模糊自我適應共振理論網路(Fuzzy ART)，將晶圓針測圖(Bin Map)與晶圓缺陷圖(Defect Map)做討論，建構各Bin值與缺陷樣版圖的辨識，並做出合理的分類的系統，提供工程師在觀察晶圓針測圖時，可找出哪一製程階段出的缺陷，同時得知還有哪些晶方處於相同情況，進而回推到錯誤率高的製程點做改善，本研究樣本為75筆141顆規格的晶方，其中55筆做為訓練，20筆為測試樣本，而實證分析結果顯示，辨識正確率達90%，系統可以成功的區分出隨機性故障圖樣，並且消除系統性故障圖樣上的雜訊，提供有用的資訊幫助提高診斷的效率。

Semiconductor industry is an industry that requires both capital and technology, it faces not only pressure from high cost and timing for entering markets, but also has a major issue regarding to its yield. As for the production line, wafer bin map provides an essential clue for identifying any abnormality in wafers. It builds up a system which points out the causes that might be accounted for having such low yield. Nowadays, the majority method for recognizing wafer bin map in the fab is done through naked human eyes. However, the distribution of wafer bin map, as well as the engineer’s personal experiences or subjective estimations, could create problems of overtime-identifying and lack of accuracy which lead to results of low efficiency when it comes to problem solving. In order to discuss the correlation between the wafer bin map and defect map, this research conducts a methodology by using Fuzzy ART algorithm. During the analyzed model, firstly, this research recognizes number of wafer bin maps and defect maps. While speculating the wafer bin map, this model allows the engineers to find out not only which the manufacturing process is mistaken but also the particular die that appears to be abnormal. Since the engineers are able to trace back the mistake where it’s being made, they can of course improve the procedure by correcting the error. The sample size of wafers to this research is 75, and each of them contains 141 dies. While 55 wafer maps are used for training, the other 20 are for testing. The analytical result shows that there is 90% of accuracy. The system is able to successfully differentiate the random malfunction, also it provides supportive information for improving the efficiency while analyzing.

中文參考文獻
王怡絜（2006)，「交錯圖形偵測應用於半導體缺陷圖樣辨識之研究」，國立清華工業工程與工程管理學系研究所碩士論文。
林寅智（1998)，「以工程資料為基礎之半導體故障分析系統」，國立清華大學工業工程與工程管理研究所碩士論文。
洪維恩（2010)，Matlab7程式設計，旗標出版股份有限公司。
張柏年（2003)，「以倒傳遞網路為基礎之自動化晶圓缺陷檢測系統」，國立清華大學工業工程與工程管理研究所碩士論文。
張家銘（2007)，「以CART決策樹方法建構晶圓良率值與晶圓允收參數間之關連性模式」，國立清華大學工業工程與工程管理研究所碩士論文。
陳逸新（2009)，「半導體研發階段WAT參數之黃金晶方抽樣分析」，國立清華大學工業工程與工程管理研究所碩士論文。
葉怡成（2009），「類神經網路模式應用與實作」，儒林圖書公司。
廖建倫（2002），「整合自適應共振理論Ⅱ神經網路與遺傳演算法為輔之K-means 於資料採礦之研究」，Journal of the Chinese Institute of Industrial Engineers, Vol. 19, No 4, pp.64-70。
謝祥文（2004)，「區域分割為基礎之晶圓缺陷圖樣辨識演算法」，國立清華大
工業工程與工程管理學系研究所博士論文。
簡禎富、施義成、林振銘、陳瑞坤（2005)，「半導體製造技術與管理」，國立清華大學出版社。
魏連均（2006)，「應用類神經網路建構晶圓圖故障圖樣辨識模式」，國立清華大學工業工程與工程管理研究所碩士論文。

英文參考文獻
Aitken, R.C. ,（2008)“Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp.46-54.
Alfredo Weitzenfeld, Michael A. Arbib, Amanda Alexander,（2002)“The Neural Simulation Language: A System for Brain Modeling”.
Berry, M. J. A. and Linoff, G.,（1997）“Data mining Technique For Marketing, Sale, and Customer Support”.
Bose, B.K., (2007)“ Neural network applications in power electronics and motor drives: An introduction and perspective,” IEEE Transactions on Industrial Electronics, Vol. 54, No. 1, pp.14-33.
Carpenter, G.A. and Grossberg, S.,（2003), Adaptive Resonance Theory, In Michael A. Arbib (Ed.), The Handbook of Brain Theory and Neural Networks, Second Edition , pp.87-90.
Carpenter, G.A. and Grossberg, S.,（1987), ART 2: Self-organization of stable category recognition codes for analog input patterns, Applied Optics, Vol. 26, No. 23, pp.4919-4930.
Carpenter, G.A. and Grossberg, S. ,（1990), ART 3: Hierarchical search using chemical transmitters in self-organizing pattern recognition architectures, Neural Networks (Publication), Vol. 3, pp.129-152.
Carpenter, G.A., Grossberg, S., and Rosen, D.B., (1991), Fuzzy ART: Fast stable learning and categorization of analog patterns by an adaptive resonance system, Neural Networks (Publication), Vol. . 4, No. 6, pp. 759-771.
Chen, F.L. and Liu, S.F.,（2000),“A Neural-Network Approach To Recognize Defect Spatial Pattern In Semiconductor Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 366-373.
Chien, C.F., Lin T.H., Peng, C.Y. and Hsu, S.C., (2001)."Developing Data Mining Framework and Methods for Diagnosing Semiconductor Manufacturing Defects and an Empirical Study of Wafer Acceptance Test Data in A wafer FAB," Journal of the Chinese Institute of Industrial Engineers, Vol. 18,No. 4, pp. 37-48.
Cunningham, S. and MacKinnon, S.,（1998）” Statistical methods for visual defect metrology,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 1, pp. 48-53.
Fayyad, U., Piatetsky-Shapiro, G., and Smyth, P.,（1996）“The KDD Process for Extracting Useful Knowledge from Volumes od Data”, Communication of ACM, Vol. 39, No.11, pp. 27-34.
Frawley, W.J., Paitetsky, S.G. and Matheus, C.J.,（1992）“Knowledge Discovery in Databases: An Overview,” Al MAGAZINE , Vol. 13, No 3, pp. 1-34.
Grupe, F.H. and Owrang, M.M.,（1995）“Data Base Mining Discovering New Knowledge and Coperative Advantage”, Information Systems Management, Vol. 12, No. 4, pp. 26-31.
Hansen, C.K. and Thyregod, P.,（1998）“Thyregod, Use of wafer maps in integrated circuit manufacturing”, Microelectronics Reliability, Vol. 38, No. 6-8, pp. 1155–1164.
Hansen, M.H., Nair, V.N. and Friedman ,F.J.,（1997）”Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects,” Technometrics, pp. 241–253.
Hwang, J.Y. and Kuo, W.,（2007）“Model-based clustering for integrated circuit yield enhancement,” European Journal of Operational Research, Vol. 178, No. 1, pp. 143-153.
Karthikeyan, M., Fox, S., Cote, W., Yeric, G., Hall, M., Garcia, J., Mitchell, B., Wolf, E. and Agarwal, S.,（2008）“A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software”, IEEE Transactions on semiconductor manufacturing, Vol. 21, No. 2, pp. 161-168.
Kikuchi, H., Nishio, N., Ikeyama, K.and Misumi, A.,（1999）“Advanced Defect-Kill-Rate Estimation and Yield Analysis incorporating defect clustering,”IEEE Transactions on semiconductor manufacturing , pp. 387 – 390.
Kleissner, C.,（1998) “Data Mining for Enterprise” IEEE Proc. 31st Annual Hawaii International Conference on System Sciences ,Vol. 7, pp. 295-304.
Kyungmee, O., Kim, W.K., Wen, L.,（2004）”A relation model of gate oxide
yield and reliability”, Microelectronics Reliability , Vol. 44, No. 3, pp. 425–434.
Layra Burke and Soheyla Kamal,（1995）“Neural Networks and the Part Family/Machine Group Formation Problem in Cellular Manufacturing:A Framework Using Fuzzy ART,” Journal of Manufacturing Systems, Vol. 14, No. 3, pp. 148-159.
Li, T.S. and Huang, C.L.（2009）“Defect spatial recognition using a hybrid SOM-SVM approach in semiconductor manufacturing,” Expert Systems with Application 36, pp. 374-385.
Mirza, A.I., O'Donoghue, G., Drake, A.W. and Graves, S.C. ,（1995）“Spatial yield modeling for semiconductor wafers,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, No.13-15, pp. 276-281.
Neyer ,T., Hafner, M.,（2004）“Yield Learning Using the Defect Reticle Method” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 110-114.
Ono, M. Iwata, H. Watanabe, K.,（2002）“Accuracy of Yield Impact Calculation Based on kill Ratio,” Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop, pp. 87-89.
Plummer, J.D., Deal, M.M. and Griffin,P.B.,（2000）“Silicon VLSI Technology Fundamentals, Practice and Models,” Prentice Hall
Rastogi, P., Kozicki, M.N. and Golshani, F.,（1993）“ExPro-an expert system based
process management system,” IEEE Transactions on Semiconductor
Manufacturing, Vol. 6 , No. 3, pp. 207–218.
Riley, Stuart,（2007）“A Simplified Approach to Die-Based Yield
Analysis,” Semiconductor International, Vol. 30, No. 9, pp. 47-51.
Rilyey, Stuart L.,（2010）“A Die-Based Defect-Limited Yield Methodology For Line Control,” IEEE Transactions on Semiconductor Manufacturing, pp. 27-33.
Su, C.T.,(2010)，”The Class Handout of Neural Network models and Applications”
Sinha, S., Su, Q., Wen, L., Lee, F., Chiang, C., Cheng, Y.K., Lin, J. and Harn, Y.C.,（20008）“A New Flexible Algorithm for Random Yield Improvement,” IEEE Transactions on Semiconductor Manufacturing, Vol. 21, No. 1, pp. 14-21.
Taam, W., Subbaiah, P. and Liddy, J. W.,（1993）“A note on multivariate capability indices, Journal of Applied Statistics,” Vol.20, No. 3, pp. 39-351.
White, K.P., Kundu, B. and Mastrangelo, C.M.,（2008）“Classification of Defect Clusters on Semiconductor Wafers Via the Hough Transformation, ”IEEE Transactions on Semiconductor Manufacturing, Vol. 21, No. 2, pp. 272-278.
Wilson,D. and Walton , A. J.,(1994) “Automatic In-line to End-of-line to End-of-line Defect Correlation Using FSRAM Test Structure for Quick Killer Defect Identification,” Proceedings of the IEEE International Conference on Microelectronics Test Structure, Vol. 7 , No. 22-25, pp. 160-163.