研究生: |
汪俊傑 Wang, Chun-Chieh |
---|---|
論文名稱: |
ECO Timing Optimization Using Spare Cells by Bounded-Delay Minimum-Cost Path Computation 利用預留元件透過限制延遲最小成本路徑計算法做工程修改命令的時序最佳化 |
指導教授: |
麥偉基
Mak, Wai-Kei |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 英文 |
論文頁數: | 31 |
中文關鍵詞: | 預留元件 |
相關次數: | 點閱:1 下載:0 |
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在現代積體電路設計中,電晶體的光罩大概佔整套光罩的68%,也就是說如果我們只改變金屬線來解決時序違規,我們就可以節省68%的光罩費用。在這篇論文中我們提出一個方法可以在工程修改命令階段解決時序違規,我們可以使用在晶片上的預留元件透過重新繞線來解決時序違規。為了處理不同路徑使用預留元件的競爭問題,我們給所有的預留元件一個費用。我們將這個時序最佳化問題轉化成一個不循環有向圖,並且我們用貝爾曼-福特限制延遲最小成本路徑演算法來解決這個問題在一些從源到尾的時間限制及最小化費用。實驗結果顯示我們的演算法能夠使用較少的預留元件來解決時序違規,我們能夠節省約29%的預留元件。
[1] Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang, “ECO Timing Optimization Using Spare Cells,” in Proceeding of International Conference on Computer-Aided Design,
2007, pp.530-535.
[2] Yen-Pin Chen. ECO TIMING OPTIMIZATION USING SPARE CELLS AND TECHNOLOGY REMAPPING, M.Sci. Thesis, Department of Electrical Engineering, National Taiwan University, July 2005.
[3] R. Ravindran. Distributed and Sequential Heuristics for QoS Routing in Communication Networks, M.Sci. Thesis, School of Computer Science, University of Oklahoma,
December 2000.
[4] Dai, H.K. and Du, Y., “On the Bounded-Delay Minimum-Cost Path Problem of Quality-of-Service Routing,” in Proceeding of Computer Communications and Networks,
2007, pp.384-390.
[5] Sachin Sapatnekar. Timing. Kluwer Academic Publishers, 2004.
[6] Michael D. Moffitt, David A. Papa, Zhuo Li and Charles J. Alpert, “Path smoothing via discrete optimization,” in Proceeding of the Design Automation Conference, 2008, pp.724-727.
[7] Modi, N.A. Marek-Sadowska, M., “ECO-Map: Technology remapping for post-mask ECO using simulated annealing,” in Proceeding of the International Conference on Computer Design, 2008, pp.652-657.
[8] Kai-hui Chang, Igor L. Markov and Valeria Bertacco, “Reap what you sow: spare cells for post-silicon metal fix,” in Proceeding of the international symposium on Physical design, 2008, pp.103-110.
[9] Doug Josephson, “The Good, the Bad, and the Ugly of Silicon Debug,” in Proceeding of International Conference on Computer-Aided Design, 2007, pp.3-6.
[10] Chien Pang Lu, Mango C.-T., Chen Hsing Lo and Chih Wei Chang, “A metal-only- ECO solver for input-slew and output-loading violations,” in Proceeding of the international
symposium on Physical design, 2009, pp.191-198.
[11] Yu-Min Kuo, Ya-Ting Chang,Shih-Chieh Chang and Marek-Sadovvska, M. “Engineering change using spare cells with constant insertion,” in Proceeding of International
Conference on Computer-Aided Design, 2007, pp.544-547.
[12] K.-H. Chang, I. L.Markov and V. Bertacco, “Automating Post-Silicon Debugging and Repair,” in Proceeding of International Conference on Computer-Aided Design, 2007,
pp.91-98.