鎖相迴路 (Phase-Locked Loops)在系統整合晶片（System on Chip）已經被廣泛的用來產生乾淨而且穩定的時脈，由於現在系統速度越來越快，以及系統也有著雜訊干擾，所以使得系統需要更嚴謹的時間規格。藉由量測鎖相迴路所產生出來時脈的抖動量(Jitter)便能判別雜訊影響的程度，進而改善鎖相迴路的效能，而不致使得整個系統整合晶片的良率受到影響。傳統的量測方式是使用外部的 ATE (Automation Testing Equipment) ,此量測方式有著量測成本昂貴且不能準確的直接量測深藏在晶片中的鎖相迴路的問題，使用內建自我量測電路 BIST(Built-in-Self-Test)以達到解決這些問題且能正確量測到鎖相迴路的抖動量。本論文提出一個量測方式及電路來直接量測到鎖相迴路的最大累積抖動，包含正和負的最大累積抖動。量測電路使用高速計數器(High-Speed Counter)對鎖相迴路輸出累積N個週期時間量,經由兩級時間對電壓轉換(Two-Stage Time-to-Voltage Conversion)對正負抖動量作個區分，峰值電壓檢測(Peak Detector)、谷值電壓檢測(Valley Detector)，以反向器為基礎的快閃類比轉數位輸出(Inverter-based Flash Analog-to-Digital Conversion)所組成。因此便能在量測過程就直接量測到最大的抖動量而不需事後決定抖動的正負之分(Without Post-Processing)。量測頻率範圍為 700MHz-1.4GHz，累積8個週期進行量測，量測得到的解析度和線性失真分別是44ps及1.25%。量測在1GHz之下再經過校正(Calibration)得到的最大誤差為一個最小計數單位(LSB)，而1GHZ以上的頻率量測得到最大誤差在1LSB--2LSB之間。

This paper presents a Time-to-Digital Converter (TDC) circuit to measure the worst-case accumulated jitters over N periods of the PLL output signal. The worst-case jitters that include the most positive jitter and the most negative jitter can be calculated through the proposed approach. For a case study, under the proposed TDC circuit, the frequency range of the measured signal, the accumulated periods, and resolution are 700MHz~1.4GHz, 8 periods, and 44ps respectively, with the 4-bit flash ADC. The HSPICE simulation result shows that the maximum measurement error is 1-LSB after calibration using a 0.25um CMOS process.

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