850nm選擇性氧化侷限垂直共振腔面射型雷射之研製

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研究生：	江文章 Wen-Jang Jiang
論文名稱：	850nm選擇性氧化侷限垂直共振腔面射型雷射之研製 The study of 850 nm selective oxide-confined vertical cavity surface emitting lasers
指導教授：	吳孟奇 Meng-Chyi Wu
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2002
畢業學年度：	90
語文別：	中文
中文關鍵詞：	氧化侷限、垂直共振腔、面射型雷射
外文關鍵詞：	oxidatuion, vertical cavity surface emitting laser, VCSEL, ITO
相關次數：	點閱：2 下載：0
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由於人們對頻寬的需求不斷持續增加，高速光纖網路的市場競爭戰火已經點燃，其中的代表就是資訊網路及乙太網路。這些系統之傳輸速率快速成長，現在已經達到了1.25Gb/s，而面射型雷射(VCSEL)已成為這些系統所採用的一種重要光源，它的頻寬已足以應付2.5Gb/s或以上的傳輸系統，甚至單一元件傳輸更可高達10Gb/s，其製程技術發展的重要改變為質子佈植(proton implantation)轉變成氧化侷限(Oxide confined)，即使用一層高鋁組成AlxGa1-xAs (x=0.98) 在高溫高溼環境中進行氧化而形成面射型雷射的發光區(aperture)，因為可以製成優異的電流侷限效果，其臨限電流遠比質子佈植型者更低，操作速度更快。
本論文主要在探討選擇性氧化侷限垂直共振腔面射型雷射之研製。首先以砷化鎵/砷化鋁鎵半導體材料為基礎，藉由改變不同折射率材料之介面組成、漸變厚度及漸變方式，設計出具有高反射率以及低元件串聯電阻之布拉格反射器，然後模擬於共振腔附近引進高鋁含量之砷化鋁鎵磊晶層於電場強度駐波結點位置做為氧化層，應用漸變折射率分離侷限異質接面結構於共振腔中以進一步降低串聯電阻，模擬出最佳特性之850nm氧化侷限垂直共振腔面射型雷射。

高鋁含量之砷化鋁鎵磊晶層的選擇性氧化為定義面射型雷射增益區之關鍵製程技術，改變高鋁含量、氧化溫度及氮氣流量等因素均會影響氧化速率，仔細探討氧化製程變因有助於建立穩定且高再現性之選擇性氧化製程技術。除此之外，我們應用可透光的銦錫氧化合金（Indium Tin Oxide, ITO）取代傳統不透光的鈦鉑金來製作P-型金屬電極，將元件結構以及雷射製程技術加以改進，使製程更為簡化而適合於大量生產，製作出具有良好發光效率之氧化侷限垂直共振腔面射型雷射。

In this thesis we first describe the difference between the edge emitting laser and the VCSEL, and we have introduced the progress of VCSELs. Since the oxide-confined VCSELs have excellent current confinement effect and many other native advantages than others, we have take our intention in the oxide-aperture current-confined VCSEL.
The theories about the oxide-aperture current-confined VCSEL have been introduced. We can maintain the effective reflectance while applying different graded interfaces with different grading methods and thickness into DBR structure. We also discuss how to align the cavity resonance and gain peak for designing a structure with better performance in higher temperature. At latter we take oxide aperture placement effect and GRINSCH structure into account and finish a VCSEL structure design.

Since the selective oxidation of AlGaAs layer is a key process technology of the oxide-confined VCSEL fabrication, we have taken some experiments to discuss the various about oxidation. We first demonstrate the oxidation process and equipment we used and state possible oxidation mechanism subsequently. We investigate some main variables affecting the oxidation rate just like the furnace temperature, the N2 flow rate, and the Al composition in oxide layer. Fortunately, we can obtain highly uniform oxide apertures by controlling the furnace temperature and the N2 flow rate accurately. The detail process to fabricate the oxide-confined VCSEL has been described latter. Some problems appear during the process have been discuss and improve. We have changed mesa structure from the air-post to the ring-trench. The almost same L-I curves of 4 neighboring chips show the highly stable process yield. We also have fabricated the oxide-confined VCSELs by filling Al metal into the ring trench of VCSELs, which can effectively increase the output power and enhance the high-temperature operation. The life-time test has improved the good output characteristics for these oxide-confined VCSELs.

While the connecting Ti-Au metal between ohmic contact and bonding pad has to cross the 5μm–depth ring trench, it is easy to being broken during the process. We have studied some new planarized structures to improve this problem. The ring-trench structure liking a letter "C" around the mesa with a 3 μm-width bridge is the best choice. We also have demonstrated the effect of indium tin oxide as a p-type ohmic contact for the 850 nm GaAs oxide-confined VCSELs with this structure. The ITO film can be formed as a good ohmic contact without any annealing and exhibits a high optical transparency and high electrical conductivity. The oxide-confined VCSELs with ITO contact can be fabricated in a much simple photolithographic process and are more suitable to the fiber connection than the edge-emitting laser.

Contents
Chapter 1 Introduction.......................................1

Chapter 2 Theory and Simulation..............................7

        2.1 DBR Theory.......................................8

        2.2 Graded Interface in DBR..........................9

          2.2.1 Graded Region Thickness Dependence..........14

        2.3 Full Device Simulation..........................15

          2.3.1 Temperature Dependence of VCSEL.............18

          2.3.2 Cavity Resonance / Gain Peak Alignment......19

        2.4 Additional Consideration in VCSEL...............21

          2.4.1 Oxide Aperture Placement Effect.............21

          2.4.2 Apply GRINSCH Structure.....................22

        2.5 Summary.........................................24

Chapter 3 Oxidation.........................................25

        3.1 Oxide Process...................................26

        3.2 Oxidation Mechanism.............................27

        3.3 Results and Discussion..........................28

        3.4 Other Factor....................................33

        3.5 Summary.........................................35

Chapter 4 850nm Oxide-Confined VCSEL Process................36

        4.1 Passivation Layer Coating.......................43

        4.2 Mesa Etching....................................44

        4.3 Metalization....................................45

        4.4 Summary.........................................47

Chapter 5 Results and Discussion............................48

        5.1 850nm Oxide-Confined VCSEL with Ring-Trench.....48

        5.2 The Improve for Ring-Trench Structure and P-Type

            Ohmic Contact...................................50

        5.3 Summary.........................................54

Chapter 6 Conclusion and Future Work........................56

References.................................................128

Table Captions

Table 1 Detail information of oxide-confined VCSEL

Figure Captions

Fig. 1.1 The schematic views of (a) the VCSEL and (b) the edge emitting laser.

Fig. 1.2 Four basic VCSEL structures (a)etched air-post, (b)ion-implanted, (c) oxide-confined, and (d) regrown buried heterostructure VCSEL’s.

Fig. 1.3 The L-I characteristics comparison of the ion-implanted VCSEL with the oxide-confined VCSEL.

Fig. 2.1 Schematic drawing of a conventional VCSEL structure

Fig. 2.2 (a) Index profile typical of a quarter-wavelength stack. (b) Index profile with graded interface layers. T is the repetition period, w is 1/2 the graded layer thickness.

Fig. 2.3 Comparison of reflectance spectrum of (a) abrupt DBR vs. 7- steps grading with Al composition gradually increase from 0.22 to 0.82 and the increment is 0.1 in each step. (b) single-step vs. 7-steps grading. (c) partially enlargement of the index of  refraction in two kinds of graded interfaces. (d) single-step grading with thickness varied from 20nm to 10nm.

Fig. 2.4 Three different grading profiles used in DBR’s. The grading profiles are linear (dashed), three linear segments per interface (doted), and uniparabolic (solid).

Fig. 2.5(a) Comparison of DBR reflectivity with abrupt interface vs. 20nm grading (b) Comparison of DBR reflectivity with abrupt interface vs. 10nm grading. (c) 21nm 7-steps grading and (d) DBR reflectivity with different doping type. The insets in the lower portion in Fig. 2.5(a)~(c) roughly illustrate the DBR graded condition.

Fig. 2.6 (a) The refractive index profile and longitudinal electric field in the vicinity of the optical cavity within a VCSEL. (b) VCSEL reflectance spectrum showing the mirror cavity resonance at 850nm. (c) The index of refraction profile and normalized E2 field of a VCSEL with abrupt DBR. (d) Partial enlargement of Fig. 2.6 (c) to emphasize the cavity portion.

Fig. 2.7 (a) Gain peak wavelength varied with the cavity temperature during the interval of 200K to 400K and cavity resonance varied with different cavity length. (b) Comparison of VCSEL reflectance spectrums with different cavity lengths.

Fig. 2.8 (a) 300Å aperture layer (Al0.98Ga0.02As) adjacent to the cavity as dashed line indicated it almost located at peak position. (b) Aperture layer spaced by Al0.92Ga0.08As and thus closer to the node position. (c) Aperture layer exactly placed at the node position.

Fig. 2.9 (a) Index of refraction profile and normalized E2 field of VCSEL contains GRINSCH structure.

(b) Partial enlargement of the cavity portion of Fig. 2.9(a).

Fig. 3.1 Illustration of oxide-confined VCSEL fabrication process.

Fig. 3.2 Oxidized VCSEL with AlAs oxide layers before planarlization and p-metallization.

Fig. 3.3 Illustration of oxidation system.

Fig. 3.4 Three-zone furnace temperature profile calibration.

Fig. 3.5 Schematic illustration of selective oxidation within VCSEL structure to form current and optical aperture.

Fig. 3.6 Illustration of oxidation length measurement

Fig. 3.7 Al0.99Ga0.01As oxidation rate under three temperatures.

Fig. 3.8 Nonlinear oxidation rate of Al0.99Ga0.01As with different temperature (a) 450℃, (b) 425℃, (c) 400℃ and (d) AlAs oxidized under 400℃.

Fig. 3.9 Al0.98Ga0.02As oxidation rate under different N2 flow rate.

Fig. 3.10 Oxidation furnace temperature deviation vs. N2 flow rate.

Fig. 3.11 Oxide aperture geometry tends to become ellipse instead of circular when N2 flow rate decreased.

Fig. 3.12 AlGaAs oxidation rate with different Al composition.

Fig. 3.13 Irregular aperture resulted from re-oxidized.

Fig. 4.1 The detail process for the ring-trench oxide-confined VCSELs.

Fig. 4.2 The schematic top view of SiNx mask with some bubble on VCSEL wafers after mask etching.

Fig. 4.3 The schematic cross-section view of the mesa sidewall on oxide-confined VCSEL wafers after mesa etching under the optimized condition.

Fig. 4.4 The schematic cross-section view of the mesa sidewall on oxide-confined VCSEL wafers after mesa etching under the chamber pressure lower from 10 to 5 mTorr.

Fig. 4.5 The schematic cross-section view of the mesa sidewall on oxide-confined VCSEL wafers after mesa etching under the RF power increases from 100 to 150 W.

Fig. 4.6 The thickness of photoresistor (a) AZ1500 and (b) AZ4620 which scanning by α–step.

Fig. 4.7 Illustration of the metal lift-off process making by photoresistor AZ5214e + LOR10A

Fig. 4.8 The thickness of photoresistor AZ5214e + AZ4620 which scanning by α–step.

Fig. 5.1 The schematic top view of the fabricated 15□m oxide-aperture current-confined GaAs VCSEL with the ring-trench structure.

Fig. 5.2 The schematic cross-section view of the fabricated oxide-confined GaAs VCSELs.

Fig. 5.3 The schematic top view of the oxide aperture on the oxide-confined GaAs VCSELs after oxidation.

Fig. 5.4 The light output power, voltage and differential quantum efficiency as a function of injected current for the 15 □m-active-diameter devices packaged in TO-46.

Fig. 5.5 The CW L-I characteristics of 4 neighboring VCSEL chips with a 15 □m-current-confined aperture.

Fig. 5.6 The L-I characteristics for the VCSEL devices, one’s trench is filled with Al metal (group A) and another is not (group B).

Fig. 5.7 The L-I characteristics of the 15 □m-aperture VCSELs with Al- filling at various temperatures. The inset figure shows the temperature dependence of threshold current for the VCSELs.

Fig. 5.8 The life-time test of the 15 □m-aperture VCSELs with Al-filling.

Fig. 5.9 The schematic top view of the 6 patterns to replace the ring-trench structure.

Fig. 5.10 The schematic top view of the oxide aperture for the 4-circles pattern on the oxide-confined GaAs VCSELs after oxidation.

Fig. 5.11 The schematic top view of the oxide aperture for the 5-circles pattern on the oxide-confined GaAs VCSELs after oxidation.

Fig. 5.12 The schematic top view of the oxide aperture for the 6-circles pattern on the oxide-confined GaAs VCSELs after oxidation.

Fig. 5.13 The schematic top view of the fabricated 4-circles pattern oxide-confined GaAs VCSELs.

Fig. 5.14 The schematic top view of the fabricated 5-circles pattern oxide-confined GaAs VCSELs.

Fig. 5.15 The schematic top view of the fabricated 6-circles pattern oxide-confined GaAs VCSELs.

Fig. 5.16 The schematic top view of the fabricated 4-shorter-interleaf-trench pattern oxide-confined GaAs VCSELs.

Fig. 5.17 The schematic top view of the fabricated 4-longer-interleaf-trench pattern oxide-confined GaAs VCSELs.

Fig. 5.18 The schematic top view of the fabricated 5-interleaf-trench pattern oxide-confined GaAs VCSELs.

Fig. 5.19 The light output power and voltage as a function of injected current for the oxide-confined GaAs VCSELs with the 6 pattern structures.

Fig. 5.20 The equivalent circuit for the oxide-confined GaAs VCSELs with the 6 pattern structures.

Fig. 5.21 The I-V characteristics of reverse bias for  the oxide-confined GaAs VCSELs with the 6 pattern structures.

Fig. 5.22 The schematic top view of the new ring-trench liking a letter “C” around the mesa on on the oxide-confined GaAs VCSELs.

Fig. 5.23 The schematic top views of the fabricated oxide-confined GaAs VCSELs with (a) Ti/Au and (b) ITO ohmic contacts.

Fig. 5.24 The reflectivity as a function of wavelength for the thickness of 1230, 1400, and 1650 Å of the ITO films coated by E-beam evaporator.

Fig. 5.25 CW light output power as a function of injected current (L-I characteristics) for the oxide-confined VCSELs with ITO and Ti/Au contacts for the 10μm-current-confined aperture.

Fig. 5.26 CW voltage as a function of injected current (V-I characteristics) for the oxide-confined VCSELs with ITO and Ti/Au contacts for the 10μm-current-confined aperture.

Fig. 5.27 The lasing spectra at a driving current 0.96 mA for the two devices.

Fig. 5.28 (a) The measured far-field pattern for the device with Ti/Au contacts at a driving current of 10 mA. (b) The measured far-field pattern for the device with ITO contacts at a driving current of 10 mA.

Fig. 5.29 The far-field pattern for the VCSEL with Ti/Au contact. The metalcontact aperture is not aligned to the oxidized aperture.

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