本研究利用tsmc 0.35μm 2P4M標準CMOS製程平台以及相容於CMOS後製程，設計及製作平面式加速度計並整合其電容感測電路。本研究先實現單軸加速度感測器進而推廣至雙軸感測器。雙軸感測共用一質量塊並預期能同時量測平面X、Y方向加速度；而元件感測介面是採用全差動式，有更高的敏感度及較佳抵抗雜訊的能力。由於感測訊號極小，因此考量雜訊干擾並建立雜訊模型和設計符合元件之電容感測介面電路。電路端設計目標為低雜訊且具有可調靈敏度之功能，並探討元件與電路整合時所需考量的議題。本研究成功地將單軸加速度計與感測電路整合，量測結果其靈敏度為6.1 mV/g。

This study presents a capacitance sensing circuit with low noise and tuned-sensitivity by integrating an in-plane microaccelerometer, included one-axis and dual-axis sensors. The dual-axis microaccelerometer is monolithic using single proof-mass to sense in-plane directions. The interface of microaccelerometer is fully-differential which is capable of reducing common-mode noise and offering higher resolution. Futhermore, this work constructs a noise model to study how to suppress the noise which influences the sensitive signal effectively. The microstructure and the capacitive sensing circuit were fabricated through tsmc 0.35 μm mixed-signal 2P4M polycide 3.3/5 V process. As a result, the microstructure with one-axis sensing is successfully integrating with capacitive sensing circuit. Experimental results showed that the whole chip sensitivity measurement is 6.1 mV/g.

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