一個使用二進位重組加權電容陣列的十位元連續漸進式類比數位轉換器

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研究生：	陳志玟 Chen, Chih-Wen
論文名稱：	一個使用二進位重組加權電容陣列的十位元連續漸進式類比數位轉換器 A 10-bit Successive-Approximation Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array
指導教授：	朱大舜 Chu, Ta-Shun
口試委員:	王毓駒 Wang, Yu-Jiu 吳仁銘 Wu, Jen-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	中文
論文頁數：	70
中文關鍵詞：	連續漸進式類比數位轉換器、加權電容
外文關鍵詞：	SAR ADC, Binary-Scaled
相關次數：	點閱：4 下載：0
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隨著科技的進步，5G通訊提供了更快的資料傳輸速度，以及更低的延遲，它應用到各個層面，家居、交通、醫療、農業，帶來了更便利的生活。而當中的類比數位轉換器是不可缺少的，他是大自然與電腦中間的橋樑，類比數位轉換器(ADC)的技術也持續不斷的在進步，往更高的解析度和速度發展。
本論文提出一個十位元每秒取樣一億四千萬次的連續漸進式類比數位轉換器(SAR ADC)，採用二進位重組加權的電容陣列架構。使用台積電65奈米1P9M製程，在供應電壓為1.2 V，輸入訊號為69.453 MHz，接近尼奎斯特頻率之下，靜態模擬得到的數據DNL及INL的分別為 -1/0.996 LSB以及 -0.998/0.723 LSB。訊噪失真比（SNDR）為59.7 dB，有效位元數（ENOB）為9.625 bits，平均消耗功率為4.117 mW，核心電路面積為0.0316平方公釐。

With the development of technology, 5G communication systems provide high data transmission speeds and low latency. It is applied to home, communication, medical treatment, and agriculture, bringing a more convenient life. The ADC is an essential block in the system. It’s an important bridge between the nature world and the computer. The technologies of ADC keep improving, toward to higher resolutions and better speeds.
A 10-bit, 140-MS/s successive-approximation analog-to-digital converter (SAR ADC) using a binary-scaled recombination weighting capacitor array is implemented in a TSMC 65 nm 1P9M CMOS technology. The supply voltage is 1.2 V. The DNL and INL are -1/0.996 LSB and -0.998/0.723 LSB respectively. The SNDR is 59.7 dB and the effective number of bits (ENOB) is 9.625 bits with input frequency is 69.453 MHz, near the Nyquist frequency. The power consumption in this work is 4.117 mW . The active area is 0.0316 mm2.

摘要    I
ABSTRACT    II
目錄    III
圖目錄    VI
表目錄    IX
第一章 緒論    1
1    研究動機    1
2    論文章節組織    2
第二章 研究背景以及相關研究介紹    3
1    專有名詞    3
1.1    解析度    3
1.2    取樣與量化    3
1.3    量化誤差(Quantization Error)    4
1.4    取樣頻率    6
2    靜態特性    6
2.1    偏差(Offset error)    6
2.2    增益誤差(Gain error)    7
2.3    微分非線性度(Differential Nonlinearity；DNL)    7
2.4    積分非線性度(Integral Nonlinearity；INL)    8
3    動態特性    9
3.1    訊噪比(SNR)    9
3.2    訊噪失真比(SNDR)    9
3.3    有效位元數(ENOB)    9
3.4    無雜訊動態範圍(SFDR)    10
3.5    動態範圍(DR)    10
3.6    總諧波失真(THD)    11
3.7    有效解析頻寬(ERBW)    11
4    類比數位轉換器比較    12
4.1    尼奎斯特定理與超取樣    12
4.2    快閃式類比數位轉換器(Flash ADC)    14
4.3    管線式類比數位轉換器(Pipeline ADC)    15
4.4    連續漸進式類比數位轉換器(SAR ADC)    16
第三章 高速類比數位轉換器設計    18
1    同步與非同步    18
2    電容切換演算法    20
2.1    傳統電容切換演算法(Conventional switching algorithm)    20
2.2    分離式電容切換演算法(Split-capacitor switching algorithm)    22
2.3    單調性切換演算法(Monotonic switching algorithm)    23
2.4    共模式電容演算法(Merged-capacitor switching algorithm)    25
2.5    回切式電容切換演算法(Switchback switching algorithm)    26
2.6    統整    28
3    錯誤容忍與校正    29
3.1    傳統二進位搜尋演算法(Conventional Binary Search)    29
3.2    非二進位搜尋演算法(Nonbinary Search)    30
3.3    具有錯誤補償的二進位搜尋演算法(Binary Search with error compensation)    32
3.4    二進位重組演算法(Binary-Scaled Recombination)    33
第四章 十位元二進位重組連續漸進式類比數位轉換器    35
1    主架構    35
2    取樣及保持電路    36
3    電容矩陣    40
3.1    電容架構選擇    40
3.2    電容矩陣權重    42
3.3    電容佈局規劃    45
4    數位錯誤校正電路    47
5    比較器    48
6    數位邏輯控制電路    53
6.1    時脈產生邏輯    53
6.2    控制邏輯    55
第五章 模擬結果及電路佈局    57
1    佈局前模擬    57
1.1    靜態參數    57
1.2    動態參數    58
1.3    功耗與模擬結果    60
2    佈局後模擬    61
2.1    佈局規劃    61
2.2    靜態參數    63
2.3    動態參數    63
2.4    功耗與模擬結果    65
第六章 結論與未來展望    67
參考文獻    68
                                

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