相較於非晶矽薄膜電晶體，低溫複晶矽薄膜電晶體其主動層擁有十分高的載子遷移率，此項優點有利於電晶體尺寸的微縮以及增加電晶體的操作速度，進而有效提高積體電路元件的密度與增加晶片的功能與設計彈性。此篇論文的研究主題是以氮化鉭為金屬閘極和氧化鋁為介電層的π形狀閘極之奈米線結構低溫複晶矽薄膜電晶體記憶體，主要應用於平面顯示器、3D堆疊結構和系統面板（SOP）的實現。
論文中利用多晶矽為主動層以降低串聯電阻；使用氧化鋁為介電層以增加記憶體的寫入抹除速度；氮化鉭為金屬閘極來抑制電子從閘極注入減慢抹除速度；多條Pi形狀之奈米線結構靠著其優異的閘極控制能力提升寫入以及抹除資料的效率。以氮化矽為儲存層，而使元件擁有在高溫 (85oC) 下極佳的資料保持能力、好的重複讀寫忍受度。，明顯指出此結構具有應用於實際產品的高度價值。
論文一部分提到，由於氮化矽為離散的缺陷，二位元操作可以實現。我們討論了兩種不同的二位元操作方法。進一步地，我們討論雙閘極的氮化鉭金屬閘極和氧化鋁介電層應用在複晶矽薄膜電晶體非揮發性記憶體。與單閘極比較，實驗結果顯示，雙閘極有較低的漏電流和較大的記憶窗(memory window)。二位元的操作也具有較小的操作電壓和讀取電壓。
在論文列出的各項數據顯示出具氮化鉭金屬閘極和氧化鋁介電層與π形狀閘極之多條奈米線結構低溫複晶矽薄膜電晶體非揮發性記憶體為一高效能記憶體且適合應用於系統整合之平面顯示器。

Compared with the amorphous-Si thin film transistors (TFTs), low-temperature poly-Si (LTPS) TFTs have higher mobility that help shrinking the transistor dimension, enhance the circuit operation speed, increase the transistor density on circuit, and add function of design capability of the circuit. The Pi-gate nanowires (NWs) with TaN metal gate and Al2O3 blocking layer were introduced to the poly-Si TFT nonvolatile memory. These devices have drawn much attention because of their wide applications on active matrix crystal displays (AMLCDs), and organic light emitting diodes (OLEDs). Furthermore, the LTPS TFTs will help to carry out three-dimensional integrated circuits (3D-ICs) for system-on–chip (SOC) and fully functional system-on-panel (SOP) applications.
In this thesis, introducing NWs channel in NVM increase gate controllability and program/erase speed (P/E) speed. The P/E speed and data retention can be improved by introducing Al2O3 high-κ blocking oxide. The erase efficiency of the TaN gate device is higher than the Poly-Si device due to the work function of the TaN is higher than the Poly-Si. The unwanted backward FN tunneling current of electron through the blocking oxide is significantly suppressed.
Because of the discrete traps of Si3N4, two-bit operation could be achieved. We discuss two kinds of two-bit operations. In addition, we discuss the dual gate poly-Si TFT NVM with Al2O3 blocking layer and TaN metal gate. Dual gate devices exhibit low leakage current in the off state and high program and erase speed due to the more edge-induced fringe electric field at each corner. A novel two-bit per cell operation is performed by modulated Fowler-Nordheim (MFN) programming and band-to-band tunneling-induced hot-hole injection (BTBT HH) erasing. The dual gate TANOS memory shows larger memory window and clear distinguish ability than single gate memory under two-bit operation

Chapter 1
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