在這篇論文裡面，我們提出了一個具有低抖動量(jitter)且操作頻率寬廣的全數位鎖相迴路(All-Digital Phase-Locked Loop)，實際晶片量測結果顯示其中的數位頻率振盪器(Digitally-Controlled Oscillator)可以操作在62MHz ~ 616MHz，再搭配上一個可程式化的除頻器，其除數的範圍為1~2046，因此可因應各種不同的應用而產生出各式不同的頻率組合。並且我們利用一個在靜態記憶體(SRAM)中經常使用的栓鎖型感測放大器(Latch-based Sense Amplifier)來作為相位偵測器(Phase Detector)，利用其放大的能力，使得其能夠有極高的解析度，模擬結果顯示，即使其相位差只有1ps並且存在製程變異時，仍能夠正確判斷且運作。除此之外，此全數位鎖相迴路透過一個漸進式的鎖定過程，以達其低抖動時脈目的；首先，利用一個預測式的鎖相方式，將相位快速鎖定；接著利用一個具壓抑性的數位濾波器(Suppressive Digital Filter)來減少時脈抖動，最後再利用一個利用頻率內差(Frequency Interpolation)的相位鎖定方式來增加數位控制振盪器的解析度，因而可再改善其相位誤差(Phase Error)與時脈抖動。此電路設計亦透過TSMC 0.18um的製程實現，模擬結果發現，這樣的鎖定方式，其時脈抖動的結果相當接近於開迴路數位振盪器的效能，同時當參考時脈頻率為1MHz且N為128時，透過頻率內差的鎖定方式，其相位誤差值可由原來588ps降低至21ps，量測的結果發現，當其輸出頻率在600MHz時，其峰對峰的時脈抖動與方均根時脈抖動分別只有56ps與7.28ps。

In this thesis we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). Measurement results show the digitally controlled oscillator (DCO) is able to operate from 62 to 616 MHz. Combined with a programmable divider with its multiplicative factor from 1 to 2046, various frequencies could be synthesized for different applications. The Phase Detector (PD) is designed using a latch-based sense amplifier, leading to a nearly perfect one that is able to resolve a phase difference as minute as 1ps, while withstanding severe process variation. This ADPLL achieves low output clock jitter by a hybrid locking procedure. Firstly, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further minimized by a suppressive digital filter. Finally, a concept of frequency interpolation is utilized to enhance the resolution of the DCO so as to further reduce the phase error and jitter. Simulation results show that the jitter performance is very close to that of the free-running DCO and the phase error can be substantially reduced from 588ps to 21 ps where the reference clock is 1MHz and N is 128. Measurement results show that the jitterPk-Pk and jitterRMS are 56ps and 7.28ps, respectively, when the output clock of the ADPLL is running at 600Mhz.

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