可以藉由在閘極上施加不同的電壓來控制穿隧通過絕緣體電流大小之金屬絕緣體穿隧電晶體已經實現出來了。在本次實驗中，使用爐管生成厚度為11 奈米(nm)閘極氧化層，接者利用電子槍蒸鍍系統鍍上奈米級厚度的金屬和金屬電極，在此時並利用二次離子質譜儀(secondary ion mass spectrometry, SIMS)以及穿透式電子顯微鏡(transmission electron microscope，TEM)照片分析來作金屬薄膜鈦(Ti)的物性方面的確認。最後，再使用接觸式原子力探針顯微儀（contact mode atomic force microscope，C-AFM）利用其導電性探針(探針尖端誘發氧化的原理)在極薄的鈦金屬薄膜(約奈米級的厚度)上作局部氧化，藉以產生金屬氧化物，用來製作金屬/絕緣體/金屬(鈦/氧化鈦/鈦，Ti/TiOx/Ti)結構，並完成金屬/絕緣層穿隧電流電晶體的製作。在電晶體中所謂的奈米尺寸之通道長度，亦即穿隧絕緣體(TiOx)的寬度為58.8 奈米，此數量級是本次實驗所得到最小的數值，利用這個樣品在通道的動態介電常數約1.7。另外，金屬絕緣體穿隧電晶體在室溫下的汲極電流對汲極電壓特性，也就是說利用閘極電壓來有效控制穿隧電流的大小，也可以從中觀察得到。但是卻發現汲極電流為汲極電壓的指數函數，換句話說，就是閘極的控制能力較汲極差。最後再利用自洽法(self-consistent method)的分析，可以得到在氧化鈦(TiOx)中的有效電子質量為0.48 m0和鈦/氧化鈦之間的能障高度為96毫電子伏特(meV)。

Metal-insulator-tunnel-transistors (MITTs) that operate by varying the gate voltage to control the current flow through a tunnel insulator were fabricated. In this work, Si/SiO2 were used as gate/gate oxide. The gate oxide layer (gate oxide thickness=11nm) is formed by thermal oxidation. Ti was used as the metal electrodes and TiOx was used as the tunnel oxide. Ti was deposited by E-Gun evaporation system. The local Ti/TiOx/Ti tunnel junctions were formed by tip-induced anodic oxidation with conducting-tip atomic force microscope (AFM). The nanometer-scale channel length is defined by the thickness of the tunnel insulator (TiOx). The thickness of TiOx was 58.8 nm and the dynamic dielectric constant (□r) of the channel insulator was extracted from Schottky emission is 1.7. The IDS-VDS characteristics of the MITT indicated that the modulation of the tunneling current by gate voltage at room temperature was observed. In addition, an analysis of self-consistent method showed that the electron effective mass in TiOx was about 0.48m0 and the extracted Ti/TiOx barrier height was about 96 meV.

[1] S. M. Sze, “Semiconductor Devices Physics and Technology,” Wiley, New York, 1985.
[2] C. K. Hiang, W. E. Zhang, and C. H. Yang, “Two-dimensional numerical simulation of schottky barrier MOSFET with channel length of 10 nm,” IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 842-848, 1998.
[3] C. Teague, “奈米技術發展近況,“ 量測資訊, vol. 80, pp. 12-13, 2001.
[4] K. Fujimaru, R. Sasajima, and H. Matsumura, “Nanoscale metal transistor control of Fowler–Nordheim tunneling currents through 16 nm insulating channel,” J. Appl. Phys., vol. 85, pp. 6912-6916, 1999.
[5] 羅士哲, 林熙翔, 和王鴻年, “掃瞄探針顯微鏡之原理與應用,“ 量測資訊, vol. 80, pp. 15-20, 2001.
[6] J. A. Dagata, J. Schneir, and H. H. Harary, “Modification of hydrogen-passivated silicon by a scanning tunneling microscope operating in air,” Appl. Phys. Lett., vol. 56, pp. 2001-2003, 1990.
[7] L. Tsau, D. Wang, and K. L. Wang, “Nanometer scale patterning of silicon (100) surfaces by an atomic force microscope operating in air, ” Appl. Phys. Lett. , vol. 64, pp. 2133-2135, 1994.
[8] P. M. Campbell, E. S. Snow, and J. S. Tsai, “Fabrication of nanometer- scale side-gated silicon field effect transistors with an atomic force microscope,” Appl. Phys. Lett., vol. 66 , pp. 1388-1390, 1995.
[9] Y. Nakamura, D. L. Klein, and J. S. Tsai, “Al/Al2O3/Al single electron transistors operable up to 30 K utilizing anodization controlled miniaturization enhancement,” Appl. Phys. Lett., vol. 68, pp. 275-277, 1996.
[10] E. S. Snow, D. Park, and P. M. Campbell, “Single-atom point contact devices fabricated with an atomic force microscope,” Appl. Phys. Lett., vol. 69, p. 269, 1996.
[11] J. T. Sheu, S. P. Yeh, C. H. Wu, and K. S. You, “Nanometer-scale patterning on titanium thin film with local oxidation of scanning probe microscope,” Nanotechnology, 2002. IEEE-NANO 2002. Proceedings of the 2002 2nd IEEE Conference on, 26-28 Aug. 2002, pp. 363-367.
[12] J. G. Simmons, “Carrier transport in thin insulator film,” J. Appl. Phys., vol. 34, p. 1793, 1963.
[13] C. Hamann, H. Burghardt, and T. Frauenheim, Electrical conduction mechanisms in solids, 1988.
[14] 李雅明, 固態電子學, 全華出版社, 1995, pp. 425-434.
[15] E. S. Snow, P. M. Campbell, R. W. Rendell, F. A. Buot, D. Park, C. R. K. Marrian,and R. Magno, “A metal/oxide tunneling transistor,” Appl. Phys. Lett., vol. 72, pp. 3071-3073, 1998.
[16] E. S. Snow, P. M. Campbell, R. W. Rendell, F. A. Buot, D. Park, C. R. K. Marrian, and R. Magno, “A metal/oxide tunneling transistor,” Semicond. Sci. Technol. vol. 13, p. A75-A78, 1998.
[17] R. Sasajima, K. Fujimaru, and H. Matsumura, “A metal/insulator tunnel transistor with 16 nm channel length,” Appl. Phys. Lett., vol. 74, pp. 3215-3217, 1999.
[18] K. Fujimaru, R. Sasajima, and H. Matsumura, “Nanoscale metal transistor control of Fowler–Nordheim tunneling currents through 16 nm insulating channel,” J. Appl. Phys., vol. 85, pp. 6912-6916, 1999.
[19] D. Wang, L. Tsau, and K. L. Wang, “Nanofabrication of thin chromium film deposited on Si(100) surfaces by tip induced anodization in atomic force microscopy,” Appl. Phys. Lett., vol. 67, pp. 1295-1297, 1995.
[20] Y. Takemura, S. Kidaka, K. Watanabe, Y. Nasu, and T. Yamada, “Applied voltage dependence of nano-oxidation of ferromagnetic thin films using atomic force microscope,” J. Appl. Phys., vol. 93, pp.7346-7348, 2003.
[21] J. Shirakashi, M. Ishii, K. Matsumoto, N. MiuRa, and M. Konagai, “Surface modification of niobium (Nb) by atomic force microscope (AFM) nano-oxidation process,” Jpn. J. Appl. Phys., vol. 35, pp. L1524-L1527, 1996.
[22] E. S. Snow, and D. Park, and P. M. Cambell, “Single-atom point contact devices fabricated with an atomic force microscope,” Appl. Phys. Lett., vol. 69, pp. 269-271, 1996.
[23] Y. Gotoh, K. Matsumoto, and T. Maeda, “Experimental and theoretical results of room-temperature single-electron transistor formed by the atomic force microscope nano-oxidation process,” J. Vac. Sci. Technol. A, vol. 18, pp. 1321-1325, 2000.
[24] B. Irmer, M. Kehrle, H. Lorenz, and J. P. Kotthaus, “Fabrication of Ti/TiOx tunneling barriers by tapping mode atomic force microscopy induces local oxidation,” Appl. Phys. Lett., vol. 71, pp. 1733-1735, 1997.
[25] K. Matsumoto, “STM/AFM nano-oxidation process to room-temperature-operated single-electron transistor and other devices,” Proc. IEEE, vol. 85, pp. 612-628, April 1997.
[26] H. R. Tsai, T. E. Hsieh, S. C. Lo, and H. H. Lin, “A study of oxide patterning on titanium thin films using scanning probe microscopy,” Nanotechnology, 2001. IEEE-NANO 2001. Proceedings of the 2001 1st IEEE Conference on, 28-30 Oct. 2001, pp. 218-222.
[27] H. Sugimura, T. Uchida, N. Kitamura, and H. Masuhara, “Nanofabrication of titanium surface by tip-induced anodization in scanning tunneling microscopy,” Jpn. J. Appl. Phys., vol. 32, pp. 363-367, 1993.
[28] K. Fujimaru and H. Matsumura, “Theoretical consideration of a new nanometer transistor using metal/insulator tunnel junction,” Jpn. J. Appl. Phys., vol. 35, p. 2090-2094, 1996.
[29] H. Scherer, T. Weimann, P. Hinze, B. W. Samwer, A. B. Zorin,and J.Niemyer, “Characterization of all-chromium tunnel junctions and single-electron tunneling devices fabricated by direct-writing multiplayer technique,” J. Appl. Phys., vol. 86, pp. 6956-6964, 1999.
[30] T. Wada, S. Haraichi, K. Ishii, H. Hiroshima, and M. Komuro, “The use of a Si-based resist system and Ti electrode for the fabrication of sub-10 nm metal-insulator-metal tunnel junctions,” J. Vac. Sci. Technol. A, vol. 16, pp.1430-1434, 1998.
[31] A practical guide to scanning probe microscopy, Park Scientfic Instruments.
[32] J. Shirakashi, K. Matsumoto, N. Miura, and M. Konagai, “Room temperature Nb/Nb oxide-based single-electron transistors,” in IEDM Tech. Dig., 1997, pp. 175-178.
[33] H. Scherer, T. Weimann, A. B. Zorin, and J. Niemyer, “The effect of thermal annealing on the properties of Al-AlOX-Al single electron tunneling transistors,” J. Appl. Phys., vol. 90, p. 2528, 2001.
[34] A. Olbrich, B. Ebersberger, and C. Boit, “Oxide thickness mapping of ultrathin Al2O3 at nanometer scale with conducting atomic force microscopy,” Appl. Phys. Lett., vol. 78, p. 2934, 2001.
[35] K. Matsumoto, M. Ishii, J. Shirakashi, K. Segawa, and Y. Oka, “Comparison of experimental and theoretical results of room temperature operated single electron transistor made by STM/AFM nano-oxidation process,” Electron Devices Meeting, 1995., International, pp. 363-366, 10-13 Dec. 1995.
[36] F. A. Buot, R. W. Rendell, E. S. Snow, P. M. Campbell, C. R. K. Marrian, and R. Magno, “Dependence of gate control on the aspect ratio in metal/metal-oxide/metal tunnel transistors,” J. Appl. Phys., vol. 84, pp. 1133-1139, 1998.
[37] R. W. Rendell, F. A. Buot, E. S. Snow, P. M. Campbell, C. R. K. Marrian, and R. Magno, “Operation and design of metal-oxide tunnel transistors,” J. Appl. Phys., vol. 84, pp. 5021-5031, 1998.
[38] F. A. Buot, R. W. Rendell, E. S. Snow, P. M. Campbell, C. R. K. Marrian, and R. Magno, “Fundamental operation and design considerations for metal-oxide tunnel transistors,” Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop, pp. 166-169, 1998.
[39] A. Shaker and A. Zekry, “Theoretical investigation of single- and dual- gate MITT nanometer transistors ,” The First Egyptian Workshop on Advancements of Electronic Devices (EWAED)., pp. 92-108, 2002.