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研究生： 柯智偉
Ke, Ji-Wei
論文名稱： 適用於三維晶片的時脈同步電路
Die-to-Die Wire-Independent Clock Synchronization for 3D IC
指導教授： 黃錫瑜
Huang, Shi-Yu
口試委員: 李鎮宜
周世傑
洪浩喬
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 40
中文關鍵詞： 三維晶片 、時脈同步電路
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    • This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-ADDLL) and a Dual Locking Mechanism, this method can be used to maintain a global clock signal between two dies in a 3D-IC, and thereby enabling the synchronous 3D-IC design methodology. Unlike previous methods, ours does not need to know the delay of the inter-die clock wire.

    現今製程技術不斷的進步下，有限平面內所能擺放的電晶體個數將因達到各元件所能容忍的最小尺寸而趨於飽和。三維晶片（3D IC）被認為可有效的解決此問題，透過垂直方向堆疊多個平面以增加擺放面積。這些垂直排列且互相平行的平面則是利用一種稱作穿矽孔（Through Silicon Via, TSV）的橋樑來進行彼此間的溝通。
    這篇論文提出了一個新式裸晶與裸晶間( die-to-die )且以全標準元件( Fully cell base )實現的時脈校正( clock synchronization )電路與方法，參考之前的論文，我們是第一個提出這樣電路架構的作品，並且電路以標準元件所組成，因此易於轉移到其它製程上，會成為其優勢。

    Abstract i 摘要 ii 致謝 iii Content v List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Thesis Organization 3 Chapter 2 Preliminaries 4 Chapter 3 Overall Circuit Architecture 6 Chapter 4 The Operating Principle of The Dual Locking Mechanism 7 4.1 Dual Locking Mechanism 9 4.2 Inverse Locking: Phenomenon 12 4.3 Inverse Locking Reslolution 15 4.4 Modified Synchronization Scheme 17 4.5 Dynamic Tracking 20 Chapter 5 Describes the proposed sub-circuit 21 5.1 2-Phase Digital Controlled Delay Line 22 5.2 Period Detector 26 5.3 Tri-State Phase Detector 29 5.4 2-Phase ADDLL Timing DIagram 31 Chapter 6 Simulation Results 32 Chapter 7 Experimental Results 33 Chapter 8 Conclusion 38 Bibliography 39

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