Contents ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES V CHAPTER 1 1 INTRODUCTION 1 CHAPTER 2 8 PREVIOUS WORK 8 CHAPTER 3 10 MODIFYING A RATE CONTROL ALGORITHM FOR HARDWARE IMPLEMENTATION 10 3.1 THE ORIGINAL RATE CONTROLLER ALGORITHM 10 3.2 STAGE REPARTIONIING 11 3.3 BEHAVIOR OF THE MODIFIED RATE CONTROL ALGORITHM 13 3.3.0 Terminologies 13 3.3.1 Behavior of the Modified Algorithm in GOP-level 15 3.3.2 Behavior of the Modified Algorithm in Frame and B.U-level 16 3.3.2.1 Target Bits Computation 16 3.3.2.2 MAD Mode Manipulation 19 3.3.2.3 RC Model Manipulation 24 3.3.2.4 QP Computation 25 CHAPTER 4 34 PROPOSED ARCHITECTURE 34 4.1 GOALS 34 4.2 A PRECISION-PRESERVING METHOD 34 4.3 RATE CONTROLLER OVERVIEW 36 4.4 RATE CONTROLLER COMPONENTS 37 4.4.1 The Architecture of Target Bits Computation 37 4.4.2 The Architecture of Model Manipulation 39 4.4.3 The Architecture of QP Computation 41 CHAPTER 5 44 EXPERIMRNTAL RESULTS 44 CHAPTER 6 49 CONCLUSIONS 49 BIBLIOGRAPHY 50 APPENDIX A1 52 List of Figures Figure 1 Block diagram of H.264/AVC Encoder System 3 Figure 2 PSNR and bit-rate of different B.U 5 Figure 3 Encoding time and bit-rate of different B.U 5 Figure 4 Flow chart of three levels Rate Controller 6 Figure 5 Flow chart of the original algorithm 11 Figure 6 Flow chart after fully parallel rearrangement 12 Figure 7 Flow chart of the modified algorithm 13 Figure 8 Example of predicting MAD by MAD Model 27 Figure 9 Example of solving the issue of predicting MAD 29 Figure 10 Original behaviors of Qstep to QP Conversion 31 Figure 11 Modified behaviors of Qstep to QP Conversion 32 Figure 12 Behaviors of QP Adjustment 33 Figure 13 Example of proposed method 35 Figure 14 Top-level block diagram of proposed RC 36 Figure 15 Block diagram of Target Bits Computation 38 Figure 16 Timing diagram of Target Bits Computation 39 Figure 17 Block diagram of Model Manipulation 40 Figure 18 Timing diagram of Model Manipulation 41 Figure 19 Block diagram of QP Computation 42 Figure 20 Timing diagram of QP Computation 43 Figure 21 Timing diagram of RC 47 List of Tables Table 1 PSNR w/ and w/o RC 2 Table 2 Three levels of RC 4 Table 3 Terminologies in RC algorithm 14 Table 4 Difference between MAD Model Update and RC Model Update 24 Table 5 Difference between MAD Model Estimation and RC Model Estimation 25 Table 6 Value to divide and multiply in Radical Computation 43 Table 7 Code coverage of RC 44 Table 8 Gate count of each function block and memory 45 Table 9 Goals and achievements 46 Table 10 Performance Comparison 48