本論文主題為設計一個利用可程式和差調變器強化頻率解析度之數位控制震盪器 (resolution-enhanced DCO)，其適用於頻段範圍介於2.4-2.5十億赫茲之無線射頻系統，包含藍芽和手機等通訊應用。此設計架構使用數位控制介面，因此避免了任何的類比控制訊號所帶來的雜訊而達到更線性穩定的輸出頻率，並且能運用於全數位式鎖相迴路 (ADPLL) 的電路設計架構之中。數位控制震盪器採用新式的切換電容設計，透過數位訊號控制三級電容切換陣列，以提供更精確的頻率解析度，達到寬廣且線性的震盪頻段。電路中所需要的最小切換電容值為30 aF,可達到10千赫茲的頻率解析度。並且利用三階可程式和差調變器高速切換電容陣列以強化頻率解析度，利用平均的概念達到最精細的頻率解析度，此可程式和差調變器利用數位控制訊號適當的修改調變器的雜訊函數。整個數位控制震盪器經過模擬後利用台灣積體電路公司的互補式金氧半(CMOS) 0.18微米製程實現，整個晶片面積為0.99 x 0.98 平方微米。量測到的頻率震盪範圍為147百萬赫茲，最小的電容切換可得到的頻率解析度為29 KHz，震盪器的相位雜訊在偏離中心載波頻率500 KHz低於 -110 dBc/Hz。利用和差調變器，頻率解析度可強化到小於3千赫茲。在供應電壓為1.8伏特的情況下，震盪器電流消耗為1.298微安培，震盪器功率消耗為3.4微瓦特。

This thesis presents the design of a novel resolution-enhanced digitally controlled oscillator (DCO) for 2.4-2.5 GHz wireless RF applications, such as 802.11b/g or cellular phones. Instead of analog tuning scheme, the DCO adopts a novel switched-capacitor network that provides sufficient tuning frequency range with fine frequency resolution. Wide and precise linear frequency tuning is achieved through digital control of three capacitor arrays. The smallest capacitance step size is approximately 30 aF that achieves the resolution of 10 KHz. The frequency resolution can be further enhanced through high-speed dithering using a third-order Σ-Δ modulator, which transfer function is programmable. The designed DCO is implemented in TSMC 0.18 μm CMOS process, and the chip area is 0.99 × 0.98 mm2. According to the measurement results, the frequency tuning range is 147 MHz. The smallest frequency step controlled by the switched-capacitor is 29 KHz. The measured phase noise is less than -110 dBc/Hz at 500 KHz offset frequency. By activating the Σ-Δ modulator, the frequency resolution is further improved, which is small than 3 KHz. The power consumption is 3.4 mW with a 1.8 supply.

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