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研究生: 王璽睿
Wang, Xi-Rui
論文名稱: 適用於多使用者之初步同步碼及其電路設計與效能分析
Large Set Construction of User Uplink Ranging Code with Analysis of System Architecture and Logic Design
指導教授: 馬席彬
Ma, Hsi-Pin
口試委員: 馬席彬
Ma, Hsi-Pin
蔡佩芸
Tsai, Pei-Yun
許騰尹
Hsu, Terng-Yin
楊家驤
Yang, Chia-Hsiang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 英文
論文頁數: 86
中文關鍵詞: 零相關區間序列初步同步物聯網雙層展頻分碼多重存取
外文關鍵詞: Zero Correlation Zone sequence, initial synchronization, Machine-to-Machine communications, two layer spreading code division multiplexing access
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  • 物聯網(Machine-to-Machine communications)的觀念以及相關應用在近幾年
    開始蓬勃發展。相關的標準制定、系統設計等等也開始被相繼提出。這篇論文中,
    我們根據新一代的物聯網通訊之需求,解決相較於以往的系統,如何允許較多使用
    者同時要求系統資源的課題。並且針對系統,實現以低複雜度為前提的電路設計。
    為了區分不同使用者的訊號,這篇論文採用分碼多重存取(Code Division
    Multiplexing Access)的概念,對每個不同的使用者分配不同的由金氏碼以及零相
    關區間碼(ZCZ)組合而成的展頻碼,相較以往發碼多重存取系統採用的偽雜訊序列
    (Pseudo-Noise)以及卡薩米序列(Kasami),都有較好的相關以及互相關特性。並以
    兩層展頻概念配合這兩種碼消除在頻域以及時域上不同的干擾,如多通道路徑干擾
    以及多存取干擾等等。利用此兩層展頻系統配合特定的展頻碼,在同時有256 個使
    用者上傳同步的環境下,錯誤率可以達到10^-3 而訊雜比為8 dB。
    最後我們根據低複雜度的考量設計出傳送端以及接收端的邏輯電路。由於零相
    關區間碼長度隨著使用者數目而增長,所以縮減這部分的面積決定傳送端的電路大
    小。而整體電路的邏輯閘數目,在0.18 μm 的製程下,大小估算為11k。同時,此
    論文提出的展頻碼系統,同步週期也較現今通訊標準來的少,根據計算,在接收端
    本論文提出之方法只需要約430 萬個週期,分別為802.16e、802.16m、以及分碼多
    重存取2000 所需的同步週期的33%、16.7%、83.9%。


    In this thesis, we present a system design for large set of user uplink codes which are suit-
    able under the scenario of large amount of users ranging in the machine-to-machine (M2M)
    communications. To distinguish from different users, spreading each user’s signals with spec-
    ified codes is one of the practical solutions. This idea is similar to the concept of code division
    multiplexing access (CDMA) system. The zero correlation zone (ZCZ) sequences and Gold
    sequences are taken as spreading sequences in the proposed CDMA-like system. The spread-
    ing procedures for each user’s signals are divided into two levels and the above codes are
    applied according to their different correlation properties to fight against different kind of in-
    terferences. Compared with previous works of traditional CDMA systems, this work supports
    a quantity of simultaneously uplink users up to 256 and is with better performance than that of
    the system accommodating only 64 users that traditional binary sequences such as Kasami or
    pseudo noise (PN) sequences are taken as spreading codes. The proposed system requires no
    additional data scrambling after two layer spreading. Instead, we take a much larger spreading
    factor. The simulation results obtained from C language programming show that the bit error
    rate of the system with proposed code assignments improves with 2 dB under SNR equals to
    10^−3 compared with the work that supports only 64 simultaneous users and requires channel
    equalization and data descrambling at the receiver end.
    The architecture and logic design of this two layer spreading system are also presented.
    The Gold sequence generator is implemented by two m-sequence generators and the ZCZ
    sequence generator is designed since there are no related works before. Besides, because
    of ZCZ sequences being taken as second layer spreading codes, the code set size of ZCZ
    sequences will decide the number of users supported which means that the code length will
    relatively become much larger. Therefore, the logic design of ZCZ sequence generator plays an important role in the size of transmitter since it takes part of 65% in the transmitter. The
    ZCZ generator design is required to be optimized to reduce unnecessary costs. The total
    gate counts of the whole system are roughly estimated about 11.k which is suitable for low
    complexity and low power consumption of M2M communications requirements, and the total
    synchronization time for the proposed code system is about 200 ms operating in chip rate of
    2.5 Mcps. Compared with IEEE 802.16e, IEEE 802.16m, and cdma2000, the synchronization
    cycles of the proposed system design are 33%, 16.7%, and 83.9% fewer.

    1 Introduction 1 1.1 Background of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Overview of Machine-to-Machine (M2M) Communications . . . . . 1 1.1.2 M2M Challenges and System Architecture . . . . . . . . . . . . . . 2 1.2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PreviousWork of Spreading Sequences Design 7 2.1 Sequence Design Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Correlation Definition . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Theoretical Limits for Spreading Sequences . . . . . . . . . . . . . . 8 2.1.3 Performance Evaluation Metrics . . . . . . . . . . . . . . . . . . . . 10 2.2 Existing Different Kinds of Orthogonal Sequences . . . . . . . . . . . . . . 10 2.2.1 Traditional Binary Sequences . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Polyphase Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 Zero Correlation Zone Sequences . . . . . . . . . . . . . . . . . . . 17 3 System Architecture Design and Analysis 25 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Two Layer Spreading System . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 Two Layer Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 Code Generation for Each Layer . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.5.1 Symbol Boundary Estimation . . . . . . . . . . . . . . . . . . . . . 45 3.5.2 Carrier Frequency Offset Analysis . . . . . . . . . . . . . . . . . . . 46 3.5.3 Sampling Clock Offset Tolerance . . . . . . . . . . . . . . . . . . . 47 3.6 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.7 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 Hardware Design 55 4.1 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Word-Length Determination . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.1 Word-length Determination . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2 Word-length in Proposed Architecture . . . . . . . . . . . . . . . . . 59 4.3 QPSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 Gold Code Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5 Zero Correlation Zone Sequence Generator . . . . . . . . . . . . . . . . . . 62 4.5.1 Basic ZCZ Sequence Construction . . . . . . . . . . . . . . . . . . . 62 4.5.2 ZCZ Sequence with Longer Zero Correlation Zone . . . . . . . . . . 66 4.6 Two Layer Spreading Transmitter and Receiver . . . . . . . . . . . . . . . . 67 5 Implementation Results 73 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 RTL Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 FPGA Emulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.1 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.2 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . 76 6 Conclusion and FutureWork 81 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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