在這個work之前，一個全數位式之鎖相迴路編譯器軟體(All-Digital Phase-Locked-Loop Compiler)已經由我們的實驗室發開出來了，然而，它仍然擁有一個使用上的限制，並且兩個潛在的問題已經經由我們的驗證被發掘出來了。所以這篇論文將它提升為一個更有製程彈性的全數位式之非整數型鎖相迴路以及改善後的編譯器軟體(Fractional-N ADPLL Compiler)。首先，我們採用了一個廣泛被使用的方法來實現非整數型鎖相迴路，除了整數倍率的功能之外，也提供了非整數倍率的特性；第二，我們對先前的全數位式之鎖相迴路它的相位追蹤能力做了一些驗證與討論，並且在其相位追蹤能力以及抖動的取捨之間做了一個決策，進而改善它對環境變異的相位追蹤能力；最後，一個有彈性的數位控制震盪器(Elastic-DCO)被呈現用來克服因PVT(P:製程、V:電壓、T:溫度)的變異所帶來的問題，特別是在使用先進製程的時候。我們也讓這個改善後的編譯器軟體去產生了許多個不同規格的全數位式之非整數型鎖相迴路，並且對它們做了三個PVT conditions的驗證，包含worst case、typical case、以及best case，實驗結果展示了我們已經成功地將之前的全數位之鎖相迴路編譯器軟體提升為一個更健全的全數位式之非整數型鎖相迴路編譯器軟體。並且當這個編譯器軟體被使用在更先進的製程時，我們所提供的方法已經事先解決了由於PVT的變異所可能會帶來的問題。

Before this work, an All-Digital Phase-Locked-Loop (ADPLL) Compiler has been developed in the previous work by our LAB. However, it still contained one restriction, and two potential problems had been found through our verification. So this work proposed a Fractional-N ADPLL which is designed to be more resilient for different processes with its improved automatic compiler. First of all, we adopt a well-known and widely-used fractional-N approach to import the fractional-N feature into our previous ADPLL. Secondly, the phase tracking ability for our previous ADPLL has been verified and discussed, which includes our decision making for the trade-off between phase tracking ability and jitter. Last but not the least, an Elastic-DCO (Digitally Controlled Oscillator) is proposed in order to overcome the PVT variation, especially for the best case when more advanced semiconductor process is used. The experimental results of many test cases show that we have successfully pushed our previous ADPLL Compiler into a more robust Fractional-N ADPLL Compiler, and provide a method to pre-solve the possible failed problem due to PVT variation when the ADPLL is used in more advanced technology.

[1] C.-W. Tzeng and S.-Y. Huang, “Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration”, IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, Mar. 2014.
[2] S.-Y. Huang, T.-H. Huang, K.-H. Tsai, and W.-T. Cheng, “A Wide-Range Clock Signal Generation Scheme for Speed Grading of a Logic Core”, IEEE International Conference on High Performance Computing & Simulation (HPCS), pp. 125-129, July 2016.
[3] A. M. Sánchez, U. Moehlmann, P. Blinzer, and M. Ehlert, “Practical design considerations for an all-digital PLL in a digital car radio reception SoC”, Central American and Panama Convention (CONCAPAN), pp. 1-5, Nov. 2016.
[4] T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma Modulation in Fractional-N Frequency Synthesis”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 5, pp. 553–559, May 1993.
[5] X. Li, J. Zheng, and L. Zhao, “Sigma-Delta Fractional-N Frequency Synthesis”, IEEE International Conference on Communication Technology (ICCT '06), pp. 1-2, Nov. 2006.
[6] W. Sun, H. Wen, and L. Gao, “A Sigma-Delta Fractional-N Frequency Synthesizer Based on ADPLL”, IEEE International Conference on Intelligent Computation Technology and Automation (ICICTA), pp. 340-342, May 2010.
[7] W. Rhee*, N. Xu*, B. Zhou**, and Z. Wang*, “Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design”, Journal of Semiconductor Technology and Science, Vol.13, No. 2, pp. 510–521, April 2013.
[8] T. V, M. Ponnambalam, and P. V. Chandramani, “Spur reduction technique for fractional-N frequency synthesizer with MASH 1-1-1-1 Sigma Delta modulator”, IEEE International Conference on Communications and Signal Processing (ICCSP), pp. 895-899, April 2014.
[9] M. Kozak, and I. Kale, “A pipelined noise shaping coder for fractional-N frequency synthesis”, IEEE Trans. on Instrumentation and Measurement, Vol. 50, No. 5, pp. 1154–1161, Oct. 2001.
[10] R. Gu, and S. Ramaswamy, “Fractional-N phase locked loop design and applications”, IEEE International Conference on ASIC, pp. 327-332, Oct. 2007.
[11] W.-C. Lai, J.-F. Huang, C.-L. Wen, and W.-T. Lay, “FPGA implementation of A MASH 1-1-1 delta-sigma modulator infractional-N phase locked loop for fuzzy control application”, IEEE International Conference on Fuzzy Systems and Knowledge Discovery (FSKD), pp. 131-134, Aug. 2014.
[12] W. Li, H. Chen, and R. Yao, “A 5.5-GHz Multi-Modulus Frequency Divider in 0.35µm SiGe BiCMOS Technology for Delta-Sigma Fractional-N Frequency Synthesizers”, IEEE International Conference on Microwave and Millimeter Wave Technology (ICMMT), pp. 1937-1940, May 2010.
[13] H.-J. Hsu, and S.-Y. Huang, “A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 1, pp. 165–170, Jan. 2011.
[14] M. Souri, M. B. Ghaznavi-Ghoushchi, and A. Abadian, “A low-power dual band all digital PLL with precision dual mode DCO and digital linearization control circuits”, IEEE Iranian Conference on Electrical Engineering (ICEE), pp. 284-289, May 2014.
[15] P.-Y. Chao, C.-W. Tzeng, S.-Y. Huang, C.-C. Weng, and S.-C. Fang, “Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 12, pp. 2240–2249, Dec. 2013.
[16] Y. Yang, W. Zhigong, T. Lu, and X. Jian, “A high precision multi-modulus fractional-N divider for DAB receiver”, IEEE International Conference on Communication Technology (ICCT), pp. 56-59, Nov. 2010.
[17] E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, “A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, pp. 824–834, Mar. 2009.
[18] D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong, “A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller”, IEEE Journal of Solid-State Circuits, Vol. 45, No. 11, pp. 2300–2311, Nov. 2010.
[19] W. Grollitsch, R. Nonis, and N. D. Dalt, “A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS”, IEEE Int. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 478-479, Feb. 2010.
[20] C.-C. Chung, D. Sheng, and C.-H. Chen, “An all-digital phase-locked loop compiler with liberty timing files”, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, April 2014.
[21] S. Kim, S. Hong, K. Chang, H. Ju, J. Shin, B. Kim, H.-J. Park, and J.-Y. Sim, “A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC”, IEEE Journal of Solid-State Circuits, Vol. 51, No. 2, pp. 391–400, Feb. 2016.