簡易檢索 / 詳目顯示

研究生: 謝旻廷
Ming-Ting Hsieh
論文名稱: 使用功能敏化路徑方法產生高品質延遲缺陷樣本
High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths
指導教授: 劉靖家
Jing-Jia Liou
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 43
中文關鍵詞: 路徑延遲錯誤小延遲缺陷功能敏化
外文關鍵詞: path delay fault, small delay defect, functional sensitizable
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 路徑延遲錯誤(Path Delay Faults, PDFs)的測試樣本通常在每個邏輯閘的邊界輸入使用靜態(static)和強健(robust)敏化規則,因此延遲缺陷影響的路徑延遲錯誤將會被這些測試樣本無條件的捕捉到。然而在功能敏化(Functional Sensitized, FS)的情形下,如果不被功能敏化的邊界輸入主控值(controlling value)所覆蓋,依然有一個種類的缺陷可以被無條件的測試。
    在這論文的第一部份,我們提供了一個新的樣本產生方法產生功能敏化路徑延遲錯誤來改善缺陷的偵測率。我們使用衝突分析來建立功能敏化決定樹。然後收尋整個樹來分析測試樣本的品質。採用這個方法得到的實驗結果表示,我們可以測到比強健或非強健(non-robust)樣本更多關鍵路徑(critical paths)的區段(有一個測試電路增加了24.03%)
    為了測試小延遲缺陷(small delay defects),轉變錯誤(transition fault)樣本產生器應該對每個錯誤用長路徑來偵測。為了達到這個目的,論文的第二部分,我們把路徑延遲測試的觀念套用在轉變錯誤樣本產生器。而這個樣本產生器會使用最長的路徑來測試小延遲錯誤。我們把論文第一部份做出的功能敏化測試的方法套用到這部份的轉變錯誤樣本產生器,去尋找最長的功能敏化路徑來測試每個轉變錯誤。實驗結果,我們比較這方法產生的功能敏化測試樣本和強健或非強健測試樣本。結果顯示,功能敏化測試樣本存在著最長的路徑來測試每個轉變錯誤。在使用功能敏化的方法下,整體平均有5.34%的轉變錯誤可以被較長的路徑測試。


    Test patterns of path delay faults (PDFs) are usually generated with static or robust sensitizing criteria for side inputs of gates, because defects affecting the delays of the PDFs will be captured by these patterns unconditionally. However, under functional sensitization (FS), there exist a class of defects that can be tested unconditionally, if they are not masked by the off-input controlling values.
    In the first part of this thesis, we propose a new pattern generation method for functionally sensitizable PDFs to improve the detectability of defects. We use conflict analysis to build a FS decision tree. Then traverse the tree for analyzing the quality of test patterns. It is shown in the experiments that with the proposed method, extra segments (up to 24.02% for one benchmark) of critical paths become testable compared with only robust/non-robust patterns.
    In order to test small delay defects, the transition fault pattern generation should test each defect with the long path. For this purpose, we apply the concept of PDFs for transition fault pattern generation in the second part of this thesis. This pattern generation searches the longest path for testing the small delay defects. We apply the FS ATPG in the first part into this transition fault pattern generation for testing each transition fault with longest FS path. In experimental results, we compare FS test patterns with robust/non-robust test patterns. It shows that FS test pattern exist the longest path for test each transition fault. In average, there are 5.34% transition faults detected with the longer path if FS is considered.

    Contents 1 Introduction 7 2 Background 10 2.1 Sensitization of Path Delay Faults . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ATPG Constraints for Sensitization . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Extended Circuit Model for FS ATPG Constraints . . . . . . . . . . . . . . . . . . 13 3 High Quality FS ATPG 15 3.1 The Quality of FS Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 FS ATPG Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Searching Necessary FS Off-Inputs . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 Learning Possible FS Off-inputs . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 Test Quality Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Proposed ATPG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 An Example of the proposed ATPG . . . . . . . . . . . . . . . . . . . . . 20 4 Incremental Constraints Transition Fault ATPG 25 4.1 Incremental Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Long Paths Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 ATPG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Experimental Results 32 5.1 FS ATPG Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Incremental Constraitns Transition Fault Experimental Results . . . . . . . . . . . 34 5.2.1 Compare Robust, Non-Robust and FS . . . . . . . . . . . . . . . . . . . . 35 5.2.2 Compare with PODEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 Conclusions 41 6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 List of Tables 2.1 Off-inputs classification of gate G on path P . . . . . . . . . . . . . . . . . . . . . 11 2.2 ATPG constraints of off-inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Path number for NR and FS sensitizations. . . . . . . . . . . . . . . . . . . . . . . 33 5.2 ATPG experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 CPU time results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 ATPG experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5 Transition fault results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6 Compare path length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7 Compare CPU time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.8 Compare with PODEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 List of Figures 1.1 An example of detectable faults under functional sensitization. . . . . . . . . . . . 8 2.1 An example of on-inputs and off-inputs. . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 An extended circuit for FS ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 An example of delay defect propagation of FS paths. . . . . . . . . . . . . . . . . 16 3.2 Different re-converge structures cause different test quality. . . . . . . . . . . . . . 16 3.3 A FS ATPG example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Search possible FS off-inputs from conflict results. . . . . . . . . . . . . . . . . . 19 3.5 An FS off-input decision tree example. . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 An example of test quality analysis. . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 The flowchart of high quality pattern generation for FS paths. . . . . . . . . . . . . 22 3.8 Apply FS ATPG constraints and find out necessary off-input f . . . . . . . . . . . . 23 3.9 Analyze ATPG results and find out conflicting off-inputs k and m. . . . . . . . . . 23 3.10 Set m as FS off-input and run ATPG. . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 Set k as FS off-input and run ATPG. . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Example of incremental constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Example of search long path method . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 Establish output node d; f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 After establishing output node i . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.5 After update nodes and remove node. . . . . . . . . . . . . . . . . . . . . . . . . 28 4.6 Conflict when adding NR constraints for off-input d. . . . . . . . . . . . . . . . . 29 4.7 Find a path c;d;h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 The flowchart of search long path method . . . . . . . . . . . . . . . . . . . . . . 31

    [1] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Boston, MA: Kluwer Academic Publishers, 1998.
    [2] K. Fuchs, H. C. Wittmann, and K. J. Antreich, “Fast test pattern generation for all path delay faults considering various test classes.” in Proceedings of European Test Conference, 1993, pp. 89–98.
    [3] K. Fuchs, M. Pabst, and T. R‥ossel, “Resist: a recursive test pattern generation algorithm for path delay faults considering various test classes.” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 13, no. 12, pp. 1550–1562, 1994.
    [4] D. Karayiannis and S. Tragoudas, “A nonenumerative atpg for functionally sensitizable path delay faults.” in Proceedings of IEEE VLSI Test Symposium, 1998, pp. 440–445.
    [5] S. Tragoudas and D. Karayiannis, “A fast nonenumerative automatic test pattern generator for path delay faults.” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 18, no. 7, pp. 1050–1057, 1999.
    [6] M. K. Michael and S. Tragoudas, “Atpg for path delay faults without path enumeration.” In ISQED, 2001, pp. 384–.
    [7] M. K. Michael, K. Christou, and S. Tragoudas, “Towards finding path delay fault tests with high test efficiency using zbdds.” in Proceedings of IEEE International Conference on Computer Design, 2005, pp. 464–467.
    [8] M. K. Michael and S. Tragoudas, “Function-based compact test pattern generation for path delay faults.” IEEE Trans. VLSI Syst., vol. 13, no. 8, pp. 996–1001, 2005.
    [9] C.-A. Chen and S. K. Gupta, “A satisfiability-based test generator for path delay faults in combinational circuts.” in Proceedings of Design Automation Conference, 1996, pp. 209–214.
    [10] J. Kim, J. Whittemore, K. A. Sakallah, and J. P. M. Silva, “On applying incremental satisfiability to delay fault testing.” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2000, pp. 380–384.
    [11] K. Chandrasekar and M. S. Hsiao, “Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation.” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2005, pp. 1002–1007.
    [12] A. Krstic and K.-T. Cheng, “Generation of high quality tests for functional sensitizable paths,” Proceedings of IEEE VLSI Test Symposium, pp. 374–379, May 1995.
    [13] R. Tekumalla and P. Menon, “Identification of primitive faults in combinational and sequential circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1426–1442, Dec. 2001.
    [14] S.-Y. Lu, M.-T. Hsieh, and J.-J. Liou, “An Efficient SAT-Based Path Delay Fault ATPG With an Unified Sensitization Model,” Proceedings of IEEE International Test Conference, pp. 1–7, Oct. 2007.
    [15] W. Qiu and D. Walker, “An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit,” Proceedings of IEEE International Test Conference, pp. 592–601, Sept. 2003.
    [16] L.-C. Wang, J.-J. Liou, and K.-T. Cheng, “Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1550– 1565, Nov. 2004.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE