晶圓層次的等溫電致遷移測試是測試在高電流大約數百倍的正常使用電流。晶圓層次的等溫電致遷移測試時間非常短，大約數十分鐘，因此晶圓層次的等溫電致遷移測試在工業界是非常便宜測試製程。本篇論文的目的利用晶圓層次的等溫電致遷移測試方法應用(1).偵測晶圓廠金屬導線缺陷(2) 金屬導線電致遷移壽命預估。
本篇論文係探討半導體晶圓廠金屬導線缺陷的偵測和金屬導線電致遷移壽命預估。晶圓層次的等溫電致遷移測試方法可以偵測晶圓廠金屬導線缺陷和金屬導線電致遷移壽命預估。晶圓層次的等溫電致遷移測試方法可以利用電阻變化率與測試時間關係圖去觀察到三相(three phases) 變化。第一相半導體晶圓廠金屬導線缺陷區，第二相金屬導線電致遷移壽命預估區和第三相金屬導線與Ti/TiN擴散層熔融區。
第一相的失效模式是半導體晶圓廠早夭期的金屬導線缺陷，所以可以利用這個機制去偵測半導體晶圓廠金屬導線缺陷。在第一相電阻變化率為快速增加到1%飽和，因此設定1%電阻變化率為第一相的失效模式的準則，去偵測晶圓廠金屬導線缺陷。第二相的失效模式是典型的金屬導線電致遷移機制，所以可以利用這個機制去預估金屬導線的壽命。在第二相電阻變化率為常數，因此遵守封裝層次金屬導線電致遷移的電阻變化率20%，所以設定1.2 %電阻變化率為第二相的失效模式的準則，去預估金屬導線的壽命。本論文利用這個準則預估金屬導線的壽命，得到晶圓層次的金屬導線的壽命比封裝層次金屬導線的壽命多三倍。第三相的失效模式是金屬導線與Ti/TiN擴散層熔融區，這是由於區域性焦耳熱造成高溫，此溫度高達2930度，導致金屬導線與Ti/TiN擴散層熔融在一起。這個現象可以從電阻變化率突然的增加發現。
晶圓層次的等溫電致遷移測試是一個快速的金屬導線認證方法，這個方法可以檢測到半導體晶圓廠金屬導線缺陷，也可以使半導體晶圓廠金屬導線有品質及可靠度的保證。同時晶圓層次的金屬導線電致遷移壽命預估比封裝層次金屬導線壽命預估又快又省錢。
內部加熱元素可以建立等溫熱元素的環境去圍繞在可以在負偏壓元件和金屬導線電致遷移結構上。這種晶圓層次的測試方法，可以應用在半導體晶圓廠金屬導線缺陷檢測和金屬導線電致遷移壽命預估。

The wafer-level isothermal electromigration (ISO-EM) test is performed at high current density that is approximately several hundred folds of the normal current density in use. The ISO-EM stress time is very short, around several tens minutes. The ISO-EM test is very low-cost process in industry. The objectives of the dissertation are to investigate (1) the detection of manufacture defects and (2) the lifetime prediction of metal interconnect of the wafer level ISO-EM test.
The detection of manufacture metal defects and the EM lifetime prediction of metal interconnect are proposed in this dissertation. The manufacture metal defects and EM failure modes can be detected by the resistance change ratio with stress time curves in wafer level ISO-EM test. The relationship between resistance change ratio and stress time has been divided into 3 phases (I, II and III) in the wafer ISO-EM test.
The failure modes of the phase I is correlated to the manufacture metal defects. The resistance change ratio of 1% is set to detect the manufacture defects in the manufacture FAB. The abnormal metal process in FAB can be detected on phase I. The failure modes of phase II are typical EM failure modes, indicating that EM occurs on phase II. The resistance change rate of 1.2% is set to predict EM lifetime. The lifetime derived from the wafer level ISO-EM test is about three times longer than that from the package level EM test. Melting at both the metal line and the diffusion barrier layer occur on phase III, which is due to local temperature higher than 2930oC (melting point of TiN) at high current density during stress. The wafer level ISO-EM test is the fast EM test process, which can be used to monitor the manufacture defects and to predict the EM lifetime. The lifetime prediction of the wafer level ISO-EM is fast and low cost compared to the package level EM test.
The concept of internal heating element can be also applied to create isothermal environment around the negative bias temperature instability (NBTI) and EM test structures for both NBTI and EM tests. The internal heating element can raise rapidly the test device structure to elevated temperature. No external heating source, such as a thermal chuck or an oven, is needed. It is a quick wafer level reliability test and can be used in in-line monitoring and screening the devices. In the wafer level EM test, poly-silicon or tungsten in various shapes can be also embedded underneath the regular metal test lines in the wafer. The poly-silicon or tungsten in various shapes act as an internal heating element, i. e. internal furnace. In this design, both current density and temperature can be controlled independently during EM stressing. No package assembly is required in the wafer level EM with embedded structure. It is useful as in-line defect monitoring and life time prediction in the manufacture fabrication process at the wafer level.

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