本次研究為雙堆疊氮化矽和環繞式閘極結構於奈米線通道非揮發性記憶體之研究，由於氧化薄化的奈米線和雙堆疊的製程，使得非揮發性記憶體的電特性有很大的進步。和傳統的記憶體相比，此種元件因製程而提升了記憶窗口、寫入和抹除速度、可靠度......等等。此製程相對容易、低成本且適用三維記憶體堆疊技術上。在本文中，我們將闡述如何製作環繞式閘極記憶體元件，及該元件的剖面圖。經過量測後發現，該元件不僅可以用FN穿隧寫入還可用熱電子注入的方式，但FN寫入的可靠度還是較好。我們還利用TCAD模擬來解釋和討論記憶體實際量測的結果和現象。我們模擬了環繞式閘極記憶體的物理模型和電性模型，發現他和實際元件有著相同的趨勢。藉由TCAD模擬的結果，我們進一步地了解到電子和電洞在元件內分布的情形，並接著解釋這些情形如何來影響我們的元件。

In this study, the “SONOS Nonvolatile Memory with Double Stacked Nitride Trapping layer and Nanowires Gate-All-Around Structure”, the characteristics of memory are improved by oxidation trimming nanowires and doubled stacked silicon nitride fabrications. Compared with conventional SONOS fabrications, these fabrications enhance the threshold voltage shift, program/erase speed, reliability......etc. Moreover, they are simple process, low cost and suitable for 3C stack memory technology.
In the thesis, we demonstrate how we fabricate the GAA SONOS device, and cross section of the device. After the measurement, we find that GAA SONOS NVM either operate in FN program or channel hot injection, but FN program shows better reliability.
We also discuss and explain some memory effects and characteristics by TCAD simulation. We simulate the physical and electrical characteristics of the GAA SONOS and find out that they have a consistent trend. By the TCAD simulation result, we further know the distribution of the trapped electrons and holes, and then we explain how these phenomena affect our NVM devices.

Chapter 1
[1-1] S. Aritome, "Advanced flash memory technology and trends for file storage application," in Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International, 2000, pp. 763-766.

[1-2] Thomas Friedman and the Fallacies of Moore’s Law
, from (https://rethinktechnology.wordpress.com/2014/01/16/thomas-friedman-and-the-fallacies-of-moores-law/).

[1-3] Crisenza, G., et al. "Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario." Solid State Device Research Conference, 1996. ESSDERC'96. Proceedings of the 26th European. IEEE, 1996.

[1-4] Global revenue from NAND Flash memory from 1st quarter 2010 to 1st quarter 2016
, from (http://www.statista.com/statistics/275889/revenue-generated-from-nand-flash-memory-by-quarter/)

[1-5] Bez, Roberto, et al. "Introduction to flash memory." Proceedings of the IEEE91.4 (2003): 489-502.

[1-6] D.Kahng, S. M. Sze, “A floating gate and its application to memory devices”, IEEE Transactions on Electron Devices,Vol. 14, pp. 629-629, 1967.

[1-7] Frohman-Bentchkowsky, “A new semiconductor charge storage device”, Solid State Electronics,Vol. 17, pp. 517-528, 1974.

[1-8] Pavan, Paolo, et al. “Flash memory cells-an overview”, Proceedings of the IEEE 85.8 (1997): 1248-1271.

[1-9] Ayling, J., R. Moore, and G. Tu. "A high-performance monolithic store." Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa. Vol. 12. IEEE, 1969.

[1-10] B. D. Salvo, “Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)”, Device and Materials Reliability,Vol. 4, pp. 377-389, 2004.
.
[1-11] J. D. Lee, “Effects of floating-gate interference on NAND flash memory cell operation”, Electron Device Letters,Vol. 23, pp. 264-266, 2002.

[1-12] S. T. Wang, "On the IV characteristics of floating-gate MOS transistors," IEEE Transactions on Electron Devices, vol. 26, pp. 1292-1294, 1979.

[1-13] C. Y. Lu, K. Y. Hsieh, “Future challenges of flash memory technologies”, Electron Device Letters,Vol. 86, pp. 283-286, 2009.

[1-14] Y. Kim, J.-G. Yun, S. H. Park, W. Kim, J. Y. Seo, M. Kang, et al., "Three-dimensional NAND flash architecture design based on single-crystalline stacked array," IEEE Transactions on Electron Devices, vol. 59, pp. 35-45, 2012.

[1-15] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, et al., "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices," in 2009 Symposium on VLSI Technology, 2009, pp. 136-137.

[1-16] J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, et al., "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," in 2009 Symposium on VLSI Technology, 2009.

[1-17] H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S. Hong, M. Wu, F. Hsu, et al., "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device," in 2010 Symposium on VLSI Technology, 2010, pp. 131-132.

[1-18] J.-G. Yun, G. Kim, J.-E. Lee, Y. Kim, W. B. Shim, J.-H. Lee, et al., "Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory," IEEE Transactions on Electron Devices, vol. 58, pp. 1006-1014, 2011.

[1-19] 奈米技術— 淺談3D NAND 快閃記憶體發展
, from (http://www.nanomark.org.tw/epaper/pdf/TANIDA-38-2.pdf)

[1-20] Samsung V-NAND technology
,from (http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf).

[1-21] S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. young Yeoh, K.-H. Hong, et al., "Gate-all-around twin silicon nanowire SONOS memory," in 2007 IEEE Symposium on VLSI Technology, 2007, pp. 142-143.

[1-22] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, "Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory," IEEE Electron Device Letters, vol. 31, pp. 216-218, 2010.

[1-23] Park, J. K., Kim, S. Y., Lee, K. H., Pyi, S. H., Lee, S. H., & Cho, B. J. “Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications”. VLSI Technology (VLSI-Technology): Digest of Technical Papers,pp. 1-2. 2014.

[1-24] Y.-R. Lin, W.-C. Wang, L.-C. Chen, and Y.-C. Wu, "Artificial Defects in Si3N4 Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors," ECS Journal of Solid State Science and Technology, vol. 5, pp. P3202-P3205, 2016.

Chapter 2
[2-1] J. S. Meena, S. M. Sze, U. Chand, and T.-Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale research letters, vol. 9, p. 1, 2014.

[2-2] P.Pavan, R. Bez, P.Olivo, E.Zanoni, “Flash memory cells-an overview”, Proceedings of the IEEE, Vol. 85, pp. 1248, 1997.

[2-3] J. Brewer and M. Gill, Nonvolatile memory technologies with emphasis on flash: a comprehensive guide to understanding and using flash memory devices: Wiley-IEEE Press, 2008.

[2-4] M. Lenzlinger and E. Snow, "Fowler‐Nordheim Tunneling into Thermally Grown SiO2," Journal of Applied physics, vol. 40, pp. 278-283, 1969.

[2-5] Sze, Simon M., and Kwok K. Ng. Physics of semiconductor devices. John wiley & sons, 2006.

[2-6] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, "Failure mechanisms of Flash cell in program/erase cycling," in Electron Devices Meeting, 1994. IEDM'94. Technical Digest., International, 1994, pp. 291-294.

[2-7] Bez, Roberto, et al. "Introduction to flash memory." Proceedings of the IEEE91.4 (2003): 489-502.

Chapter 3
[3-1] Y.-R. Lin, W.-C. Wang, L.-C. Chen, and Y.-C. Wu, "Artificial Defects in Si3N4 Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors," ECS Journal of Solid State Science and Technology, vol. 5, pp. P3202-P3205, 2016.

Chapter 4
[4-1] Synopsys, “Sentaurus Technology Template: SONOS Read/Write Operation” 2007.

[4-2] E. Nowak, A. Hubert, L. Perniola, T. Ernst, G. Ghibaudo, G. Reimbold, et al., "In-depth analysis of 3D silicon nanowire SONOS memory characteristics by TCAD simulations," in 2010 IEEE International Memory Workshop, 2010, pp. 1-4