適用於行動式都會型寬頻無線網路之多重輸入輸出基頻處理器

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研究生：	吳俊杰 Wu, Chun-Chieh
論文名稱：	適用於行動式都會型寬頻無線網路之多重輸入輸出基頻處理器 A Downlink MIMO Baseband Processor for Mobile WiMAX Communications
指導教授：	馬席彬 Ma, Hsi-Pin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	89
中文關鍵詞：	都會型寬頻無線網路、基頻、正交分頻多工存取、多輸入多輸出、同步、元件可程式邏輯閘陣列
外文關鍵詞：	WiMAX, Baseband, OFDMA, MIMO, Synchronization, FPGA
相關次數：	點閱：2 下載：0
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近來，由於正交分頻多工（OFDM）擁有良好的頻譜效率，越來越多的新一代無線通信系統採用作為其傳輸方式。此外正交分頻多工存取（OFDMA）的結合OFDM和分頻多重存取 (FDMA)系統中，使OFDM系統對於通道頻帶管理有更好的靈活性和效率。此外多輸入多輸出（MIMO）技術，在有限的通道頻帶上大大提高系統的性能或資料傳輸速度。因此，新一代的高速無線通訊透過結合MIMO和OFDMA技術進而獲得這些優勢。在這論文中，提出一系統設計和硬體實現的4 x 4 MIMO - OFDMA的下行收發機。在所提出收發機中包括符號定時同步塊、載波頻率偏移（CFO）估測和補償器、相位補償器、通道估測器、MIMO偵測器和空頻分組碼（SFBC）解碼器。在符號定時同步塊中，實現一低複雜結構的延遲相關器和有量化係數的匹配濾波器與。此外為了節省硬體成本，我們實現出一硬體共用的邊界探測器 /整數CFO估測器。而提出的分數CFO估測與補償器利用坐標旋轉數字計算機（CORDIC）反正切和CORDIC-餘弦架構取代了用唯讀記憶體 (ROM) 實現的查找表，CORDIC演算法不僅大大地減少ROM的使用，而且對於CFO和取樣頻率偏移（SFO）的估側具有較高的準確度。而通道估測器利用線性插值係數近似技術和應用的減少了硬體的複雜度但仍然有高效能。而所提出 4 x 4的MIMO - OFDMA的下行收發機支援空間多工技術的MIMO偵測器和SFBC技術的SFBC解碼器。在靜態或較低車速的環境中，相較於單輸入單輸出（SISO）系統，利用空間多工的MIMO系統能夠獲得更多的容量增益，增加更多的資料吞吐量。在高速的環境中，相較於SISO系統，MIMO系統使用SFBC模式可以提供更多的分集增益，以對抗載波間干擾（ICI）的影響所導致的多普勒效應。根據模擬結果，所提出的 4 x 4的MIMO - OFDMA的下行收發器在SFBC模式能夠在操作在300km/hr的高速環境中。最後，所提出接收機架構在Altera Stratix Ⅱ EP2S180版進行仿真並且整合進ARM SoC平台。

Recently, more and more next-generation wireless communication systems adopt orthog-onal frequency division multiplexing (OFDM) as their transmission scheme due to its good spectrum efﬁciency. Furthermore, orthogonal frequency division multiple access (OFDMA) combines OFDM and frequency division multiple access (FDMA) and making OFDM systems more and more flexibility and efficient in managing the channel bandwidth. Besides, multi-input multi-output (MIMO) techniques enhance the system performance or data rate greatly under limited channel bandwidth. As a result, by combing MIMO and OFDMA, new high-speed wireless communications enjoy the benefits from both technologies. In this thesis, the system design and hardware implementation of a 4x4 MIMO-OFDMA downlink transceiver is proposed. The proposed transceiver consists of a symbol timing synchronization block, a carrier frequency offset (CFO) estimator and compensator, a phase compensator, a
channel estimator, a MIMO detector, and a space-frequency block codes (SFBC) decoder. In the symbol timing synchronization block, the low complexity architecture of the delay-and-correlator and the matched filters with quantized coefﬁcients are proposed. Furthermore, in or-
der to save hardware cost, we implement the hardware-shared boundary detector/integer CFO estimator. The proposed fractional CFO estimator and compensator substitute the COordinate Rotation DIgital Computer (CORDIC) arctangent and CORDIC sin-cosine architecture for the loop-up table implemented by read-only memory (ROM). The CORDIC not only decreases ROM utilization greatly but also has high degree of accuracy for the CFO and sampling frequency offset (SFO) estimation. Linear interpolation and coefficient approximation technique are applied in channel estimation for reducing hardware complexity but still with high perfor-
mance. The proposed 4x4 MIMO-OFDMA downlink transceiver supports spatial multiplexing for the MIMO detector and SFBC technique for the SFBC decoder. In the static or low mobility environment, adopting the spatial multiplexing in the MIMO system could acquire more capacity gain and increase more data throughput compared with the single-input single-output (SISO) system. In high mobility environment, theMIMO system using the SFBC mode could provide more diversity gain than the SISO system to against the inter-carrier interference (ICI) effect induced by Doppler Effect. The proposed 4x4 MIMO-OFDMA downlink
transceiver in SFBC mode can operate in 300km/hr high mobility environment according to the simulation result. Finally, the proposed receiver architecture is emulated in Altera Stratix II EP2S180 board and integrated into Advanced RISC Machine (ARM) system on chip (SoC) platform.

Contents
Introduction 1
1 Introduction to WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 IEEE 802.16 and WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Descriptions 5
1 Introduction to OFDM and OFDMA . . . . . . . . . . . . . . . . . . . . . . 5
1.1 OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 OFDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 MIMO Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Array Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Diversity Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Capacity Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Beamforming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Introduction to IEEE 802.16e Physical Layer . . . . . . . . . . . . . . . . . 8
3.1 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Preamble Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Data symbol Structure . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 System Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Architecture Design 15
1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Data Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Space Frequency Block Code Encoder . . . . . . . . . . . . . . . . . 17
2.3 Pilot Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Inverse Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . 19
2.5 Cyclic Preﬁx Insertion . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Symbol Timing Synchronization Block . . . . . . . . . . . . . . . . 22
3.2 Fractional CFO Estimator and Compensator . . . . . . . . . . . . . . 25
3.3 Window Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Integer CFO Estimator and Compensator . . . . . . . . . . . . . . . 27
3.6 Phase Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Channel Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 MIMO Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 SFBC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10 Demapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 Static Channel with ITU-VA . . . . . . . . . . . . . . . . . . . . . . 39
4.2 Mobile Channel with ITU-VA . . . . . . . . . . . . . . . . . . . . . 40
5 Word-Length Determination . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Logic Design 47
1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2 Frame Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3 Boundary Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.4 Fractional CFO Estimator and Compensator . . . . . . . . . . . . . . 51
2.5 Window Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7 Integer CFO estimator and compensator . . . . . . . . . . . . . . . . 60
2.8 Phase Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.9 Subcarrier De-allocation . . . . . . . . . . . . . . . . . . . . . . . . 63
2.10 Channel Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.11 MIMO Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.12 SFBC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3 Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
FPGA Emulation and SoC Platform Optimization 75
1 Veriﬁcation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.1 FPGA Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.2 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4 Emulation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.5 FPGA Emulation Result . . . . . . . . . . . . . . . . . . . . . . . . 80
3 ARM SoC Platform Optimization . . . . . . . . . . . . . . . . . . . . . . . 81
Conclusion and FutureWork 85
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

                                

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