Nonvolatile flash memory is very popular for portable electronics, and the demand for memory density multiplies every year. Although flash memory is aggressively scaled for high-density applications, continuing to scale according to Moore’s law is becoming increasingly difficult because of both process and device limitations. This three-dimensional (3D) multi-layer-stack memory that is based on poly-Si TFTs can be a good solution for ultra-high-density memory. SONOS-type NVM with hybrid Si3N4/Si-NC/ Si3N4 trap layer can improve the retention and endurance Hence, we first investigate NWs TFT NVM using Si3N4/Si-NC/Si3N4 hybrid trap layer with excellent performance and COMS compatible process for future 3D stack NVM application.
This work demonstrates a Nanowires (NWs) poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory (NVM) that utilizes Si3N4/Si-nanocrystal (Si-NC)/Si3N4 hybrid trap layer for 3D Flash memory. The NWs poly-Si TFT NVM has high program/erase (P/E) efficiency and large memory window due to its superior gate control. Utilizing Si3N4/Si-NC/Si3N4 hybrid discrete trap layer, the NVM exhibits excellent high–temperature (150oC) retention (>108 for 6% charge loss), up to 104 P/E cycles, and two-bit operation due to its discrete trap and quantum confinement effect.

Reference
Chapter 1
[1-1] H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsunii, T. Nishimura, K. Ananii, Y. Kohno, and 11. Miyoshi, “An asymmetric memory cell using a C-TFT for ULSI SRAM,” Symp. On VLSI Tech., pp.38, 1992.
[1-2] E. Harari, L. Schmitz, B. Troutman, S. Wang, H. Co, and C. Newport Beach “A 256 bit nonvolatile static RAM,“ IEEEE ISSCC Tech. Dig., p.108, 1978.
[1-3] K. Kahng and S. Sze, "A floating gate and its application to memory devices," IEEE Transactions on Electron Devices, vol. 14, pp. 629-629, 1967.
[1-4] S. M. Sze, ‘Physics of Semiconductor Devices,” 2nd Edition, John Wiley and Sons, p.504, 1983.
[1-5] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Letters, vol. 21, pp. 543-545, 2000.
[1-6] J. Bu and M. White, "Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices," IEEE Electron Device Letters, vol. 22, pp. 17-19, 2001.
[1-7] F. R. Libsch and M. H. White, “Charge transport and storage of low programming voltage SONOS/MONOS memory devices,” Solid-State Electron., Vol. 33, pp. 105—126, 1990.
[1-8] M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans. Comp., Packag., Manufact. Technol. A, Vol. 20, pp. 190—195, June 1997.
[1-9] E. Suzuki, H. Hayashi, K.. Ishii, and Y. Hayashi, “A low-voltage alterable EEPROM with metal-oxide-nitride-oxide-semiconductor (MONOS) structures,” IEEE Trans. Electron Devices, Vol. 30, p. 122, Feb. 1983.
[1-10] M. K. Cho and D. M. Kim, “High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology,” IEEE Electron Device Letters, Vol. 21, No. 8, Aug 2000.
[1-11] B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, A. Modelli, W. Inc, and C. Fremont, “Multilevel flash cells and their trade-offs,” IEDM Tech. Dig., pp. 169—172, 1996.
[1-12] Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei, “High-performance nonvolatile HfO2 nanocrystal memory,” IEEE Electron Device Letters, Vol. 26, No. 3, pp. 154-156, Mar. 2005.
[1-13] D. Montanan, J. Van Houdt, D. Wellekens, CI Vanhorebeek, L. Haspeslagh, L. Deferm, C. I. Groeseneken, H. E. Maes, “Multi-level charge storage in source-side injection flash EEPROM,” IEEE Nonvolatile Memory Technology Conference, pp.80-83, Jun. 1996.
[1-14] G. Puzzilli and F. Irrera, "Data retention of silicon nanocrystal storage nodes programmed with short voltage pulses," IEEE Transactions on Electron Devices, Vol. 53, pp. 775-781, 2006.
[1-15] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” IEDM Tech. Dig., pp. 521-524, Dec. 1995.
[1-16] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. Crabbe, and K. Chan, "A silicon nanocrystals based memory," Applied Physics Letters, vol. 68, p. 1377, 1996.
[1-17] J. De Blauwe, A. Syst, and M. Hill, "Nanocrystal nonvolatile memory devices," IEEE Transactions on Nanotechnology, Vol. 1, pp. 72-77, 2002.
[1-18] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage” IEDM Tech. Dig., p.521, 1995.
[1-19] R.A. Rao, R.F. Steimle, M. Sadd, C.T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S.G.H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E.J. Prinz, B.E. White Jr., R. Muralidhar, “Silicon nanocryslal based memory devices for NVM and DRAM applications,” Solid-State Electron., Vol. 48, pp. 1463—1473, 2004.
[1-20] C. M. Compagnoni, D. lelmini, A. S. Spineflit, A. L. Lacaita, C. Previtali and C. Gerardil, “Study of .data retention for nanocrystal Flash memories,” Reliability Physics Symposium Proceedings, 2003. 41st Annual. IEEE International, pp. 506 - 512, April 2003.
[1-21] J. Welser, S. Tiwari, S. Rishton, K. Lee, Y. Lee, I. Center, and Y. Heights, "Room temperature operation of a quantum-dot flash memory," IEEE Electron Device Letters, vol. 18, pp. 278-280, 1997.
[1-22] H. Lue, S. Wang, E. Lai, M. Wu, L. Yang, K. Chen, J. Ku, K. Hsieh, R. Liu, and C. Lu, "A novel p-channel NAND-type flash memory with 2-bit/cell operation and high programming throughput (> 20 MB/sec),” IEDM Tech. Dig., 333, 2005.
[1-23] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, S. C. Lee, C. P. Lu, S. Y. Wang, L. W. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, J. Ku, R. Liu, and C. Y. Lu, “A highly stackable thin-film transistor (TFT) NAND-type flash memory,” in VLSI Symp. Tech. Dig., pp. 56–57, 2006.
[1-24] A. Walker, S. Nallamothu, E. Chen, M. Mahajani, S. Herner, M. Clark, J. Cleeves, S. Dunton, V. Eckert, and J. Gu, “3D TFT-SONOS memory cell for ultra-high density file storage applications,” VLSI Tech. Dig., pp. 29-30, 2003.
[1-25] Y. H. Lin, C. H. Chien, T. H. Chou, T. S. Chao, and T. F. Lei, "Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate," IEEE Transactions on Electron Devices, vol. 54, pp. 531-536, 2007.
[1-26] Y. C. Wu, T. C. Chang , P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C. Y. Chang, ‘“High-Performance Polycrystalline Silicon Thin-Film Transistor with Multiple Nano-Wire Channels and Lightly-Doped Drain Structure”. Appl. Phys. Lett., vol. 84, pp. 3822-3824, 2004.
[1-27] J. D. Choe, S. H. Lee, J. J. Lee, E. S. Cho, Y. Ahn, B. Y. Choi, S. K. Sung, J. No, I. Chung, K. Park, and D. Park, “Fin-type field-effect transistor NAND flash with nitride/silicon nanocrystal/nitride hybrid trap layer,” Jpn. J. Appl. Phys., vol. 46, no. 4B, pp. 2197–2199, 2007.
[1-28] S. Choi, H. Choi, T.W. Kim, H. Yang, T. Lee, S. Jeon, C. Kim, and H. Hwang, “High Density Silicon Nanocrystal Embedded in SiN Prepared by Low Energy (<500eV) SiH4 Plasma Immersion Ion Implantation for Non-volatile Memory Applications” , IEDM Tech. Dig., p.166, 2005.
[1-29] G. Molas, M. Bocquet, J. Buckley, J. P. Colonna, L. Masarotto, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, P. Brianceau, L. Vermande, P. Scheiblin, M. Gely, A. M. Papon, G. Auvert, L. Perniola, C. Licitra, T. Veyron, N. Rochat, C. Bongiorno, S. Lombardo, B. De Salvo, and S. Deleonibus, “Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications” , IEDM Tech. Dig., p.453, 2007.
[1-30] T. Y. Chiang, T. S. Chao, Y. H. Wu, and W. L. Yang, "High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals," IEEE Electron Device Letters, vol. 29, pp. 1148-1151, 2008.

Chapter 2
[2-1] T. Y. Chan, K. K. Young, C. Hu, “A True Single Transistor Oxide-Nitride-Oxide EEPROM”, IEEE Electron Device Letters, EDL-8, No- 3, pp. 93-95, 1987.
[2-2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview,” Proceedings of IEEE, Vol. 85, pp. 1248, 1997.
[2-3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, ch. 3, p.59, 1991.
[2-4] Stanley Wolf, “Silicon Processing for The VLSI ERA”, Vol.3, pp.435.
[2-5] M. Lenzlinger, “Fowler-Mordheim Tunneling in thermal grown SiO2,” Appl. Phys. Lett., Vol. 40, pp. 278-283, 1969.
[2-6] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-State Circuits, Vol. 14, pp. 442, 1979.
[2-7] I. C. Chen, C. Kaya and J. Paterson, “Band-to-band tunneling induced substrate hot-electron (BBISHE) injection: A new programming mechanism for nonvolatile memory devices,” IEDM, pp.263, 1989.
[2-8] K. San, C. Kaya, and T. Ma, "Effects of erase source bias on Flash EPROM device reliability," IEEE Transactions on Electron Devices, vol. 42, pp. 150-159, 1995.
[2-9] S. Chung, C. Yih, S. Cheng, and M. Liang, "A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles," IEEE Transactions on Electron Devices, vol. 46, pp. 1883-1889, 1999.
[2-10] B. Eitan, "Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping," U.S. Patent 6,011,725, Jan.4 2000.
[2-11] I. Bloom, P. Pavan, and B. Eitan, "NROMTM––a new technology for non-volatile memory products," Solid State Electronics, vol. 46, pp. 1757-1763, 2002.
[2-12] C. Swift, G. Chindalore, K. Harber, T. Harp, A. Hoefler, C. Hong, P. Ingersoll, C. Li, E. Prinz, and J. Yater, "An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase," International Electronics Device Meeting (IEDM), pp. 927-930, 2002.
[2-13] Y. Wang, Y. Zhao, B. Khan, C. Doherty, J. Krayer, and M. White, "A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase," Solid State Electronics, vol. 48, pp. 2031-2034, 2004.
[2-14] U.S. Patent 6,011,725 “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”
[2-15] W. J Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C.C. Liu, C. H. Chen, Tahui Wang, Sam Pan and Chih-Yuan Lu, “Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell,” IEEE 40th Annual International Reliability Physics Symposium, pp. 34-38, 2002.
[2-16] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” in IEDM Tech. Dig., pp. 32.2.1–32.2.4, 2001.
[2-17] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti, “New technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, pp. 73–80, 2001.
[2-18] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, pp. 1–6, 2002.
[2-19] Jan F. Van Houdt, Dirk Wellekens, Guido Groeseneken, and Herman E. Maes,” Investigation of the Soft-Write Mechanism in Source-Side Injection Flash EEPROM Devices” IEEE ELECTRON DEVICE LETTERS, Vol. 16, No. 5, MAY 1995.