在本論文提出完全不需要額外光罩的邏輯製程相容非對稱電晶體，其在正向及反向讀取電流上有明顯之差異，並利用此非對稱電晶體用於靜態隨機存取記憶體，驗證讀取與寫入的特性均可獲得提升。
非對稱電晶體的形成主要是改變邏輯製程中 LDD 及 Pocket 離子佈植的區域，利用 LDD 光罩阻擋元件汲極端的摻雜，在主動區域形成源極與汲極離子摻雜濃度分佈結構不同之非對稱元件。本研究除了設計及實作此非對稱電晶體，並分析其不對稱之電流特性及建立元件模型。
同時，將此非對稱電晶體用於靜態隨機存取記憶體中的兩個存取電晶體，使靜態隨機存取記憶體在讀取操作時，擁有比一般同規格之正常元件較小的電流，以減少讀取干擾，增加記憶體的讀取靜態雜訊邊界，降低讀取錯誤的機會。並在寫入操作時，此非對稱元件擁有比一般同規格之正常元件較大的電流，增加寫入雜訊邊界，使靜態隨機存取記憶體寫入資料更加穩定。

In this paper, a new asymmetric full logic-compatible transistor which has significant difference between forward-read and reverse-read current has been proposed. This asymmetric device is apply to Static Random Access Memory ( SRAM ) cells, enhancing their read and write performance.
Asymmetric transistor is generally formed by changing the doping level of LDD, pocket implant on one side of a MOSFET. By block the LDD and pocket implant at the drain side with the LDD mask, an asymmetric device with different drain and source doping structure can be obtained. In addition to designing and implementing the asymmetric transistor, this study analyzes its current characteristics. From that, a device model describing the asymmetric behavior is built.
Then, in order to reduce the read disturb and promote write capability, two access transistors in a SRAM cell is replaced by the asymmetric transistors. Lower accessing current in SRAM read operation, increases the Read Static Noise Margin ( RSNM ) and decreases the opportunity of read disturbs. In the meanwhile, asymmetric device as the access transistor can provide larger current during write operation, which increases the Write Noise Margin ( WNM ) and leads to more stable data.

[1] A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, and K. Chin, “Fluctuation limits & scaling opportunities for CMOS SRAM cells,” in IEDM Tech. Dig., 2005, pp. 659–662.
[2] E. Seevinck, F. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. SSC-22, no. 5, pp. 748–754, Oct. 1987.
[3] Leland Chang*, David M. Fried†, Jack Hergenrother, Jeffrey W. Sleight†, Robert H. Dennard, Robert K. Montoye, Lidija Sekaric, Sharee J. McNab, Anna W. Topol, Charlotte D. Adams, Kathryn W. Guarini, and Wilfried Haensch, “Stable SRAM Cell Design for the 32 nm Node and Beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers.
[4] Jae-Joon Kim, Aditya Bansal, Rahul Rao et al., “Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors,” IEEE Electron Device Letters, Vol. 30, No. 8, pp. 852-854, Aug., 2009.
[5] T. N. Buti, S. Ogura, N. Rovedo, and K. Tobimatsu, “A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer N-MOSFET design for reliability and performance,” IEEE Trans. Electron Devices, vol. 38, no. 8, pp. 1757–1764, Aug. 1991.
[6] T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi, and M. Bohr, “Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices,” in VLSI Symp. Tech. Dig., 2001, pp. 17–18.
[7] J. Buller, R. vanBentum, J. Cheek, E. Ehrichs, M. Horstmann, and S. Searles, “Opportunities and challenges in asymmetric device implementation,” in Proc. Custom Integr. Circuits Conf., 2004, pp. 229–232.
[8] T. Y. CHAN, A. T. WU, P. K. KO, CHENMING HU, AKD REDA R. RAZOUK, MEMBERIE, EE, “Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFET's,” IEEE ELECTRON DEVICE LETTERS, VOL. EDL-7, NO. 1, JANUARY 1986.
[9] A. Hiroki, S. Odanaka, and A. Hori, “A high-performance 0.1-_m MOSFET with asymmetric channel profile,” in IEDM Tech. Dig., 1995, pp. 439–442.
[10] S. Odanaka and A. Hiroki, “Potential design and transport property of 0.1-_m MOSFET with asymmetric channel profile,” IEEE Trans. Electron Devices, no. 5, pp. 595–600, May 1997.
[11] A. Bansal and K. Roy, “Asymmetric halo CMOSFET to reduce static power dissipation with improved performance,” IEEE Trans. Electron Devices, vol. 52, no. 3, pp. 397–405, Mar. 2005.
[12] H. Shin and S. Lee, “An 0.1μm asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability,” IEEE Trans. Electron Devices, vol. 46, no. 4, pp. 820–822, Apr. 1999.
[13] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, “High transconductance and velocity overshoot in NMOS devices at the 0.1 _m gate-length level,” IEEE Electron Device Lett., vol. 9, pp. 464–466, Sept. 1988.